Apparatus and method for stacking integrated circuits

Abstract

A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.

What is claimed is:  
     
         1 . A chip stack assembly comprising: 
 a substrate that defines a plurality of surface mount pads;    a first chip having a first set of contacts extending outward;    a second chip having a second set of contacts extending outward therefrom;    at least one support member positioned on the substrate having a first surface with a first set of mounting pads positioned thereon and a second surface having a second set of mounting pads positioned thereon wherein the first and second surfaces are displaced from each other by a first distance in a first direction and wherein the first set of contacts are attached to the first set of mounting pads and the second set of contacts are attached to the second set of mounting pads such that the first and second chips are supported so as to be displaced from each other in the first direction,    and wherein the at least one support member further includes at least one interconnect that interconnects at least one contact of the first and second set of contacts so as to electrically interconnect the at least one contact of first and second set of contacts and wherein the at least one support member further includes at least one via connection that extends in the first direction through the at least one support member to the substrate so that at least one individual contact of the first set of contacts can be electrically coupled to the surface mount pad of the substrate while being electrically isolated from the second set of contacts.    
     
     
         2 . The assembly of  claim 1 , wherein the first and second surfaces of the at least one support member are substantially parallel to each other.  
     
     
         3 . The assembly of  claim 1 , wherein the at least one support member comprises a plurality of support members.  
     
     
         4 . The assembly of  claim 1 , wherein the at least one support member comprises a printed circuit board.  
     
     
         5 . The assembly of  claim 1 , wherein the at least one via connection comprises: 
 a conductive trace positioned on the first surface that is electrically coupled to the mounting pad that is coupled to the individual contact of the first set of contacts;    a conductive element extending through a via opening formed between the first and second surfaces of the at least one support member so as to be electrically connected to the conductive trace;    a solder bump formed on the second surface of the at least one support member adjacent the via opening so as to be electrically connected to the conductive element, and wherein the solder bump is positioned so as to be electrically coupled to the surface mount pad of the substrate.    
     
     
         6 . The assembly of  claim 1 , wherein the at least one interconnect that interconnects at least one contact of the first and second set of contacts comprises a via interconnection that extends through the at least one support structure.  
     
     
         7 . The assembly of  claim 1  further comprising: 
 a third chip having a third set of contacts extending outward therefrom;  
 a second support member positioned on the at least one support member, the second support member having a third surface with a third set of mounting pads positioned thereon and a fourth surface having a fourth set of mounting pads positioned thereon wherein the third and fourth surfaces are displaced from each other by the first distance in the first direction and wherein the first set of contacts are attached to the third set of mounting pads and the third set of contacts are attached to the fourth set of mounting pads such that the first and third chips are supported so as to be displaced from each other in the first direction,  
 and wherein the second support member further includes at least one interconnect that interconnects at least one contact of the first and third set of contacts so as to electrically interconnect the at least one contact of first, second, and third set of contacts,  
 and wherein the at least one support member further includes a second via connection that extends in the first direction through the at least one support member to the substrate and wherein the second support member further includes at least one via connection that extends in the first direction through the second support member, to the second via of the at least one support structure to the substrate so that at least one individual contact of the third set of contacts can be electrically coupled to the surface mount pad of the substrate while being electrically isolated from the first and second set of contacts.  
 
     
     
         8 . The assembly of  claim 7  wherein the at least one via connection and the second via connection are displaced from each other by a second distance in a second direction and whereby the second direction is substantially perpendicular to the first direction.  
     
     
         9 . A method of mounting a plurality of chips into a stacked configuration, the method comprising: 
 attaching a first set of contacts of a first chip to a first set of mounting pads formed on a first surface of a support structure;    attaching a second set of contacts of a second chip to a second set of mounting pads formed on a second surface of the support structure, wherein attaching the first and second sets of contacts to the support structure results in the first and second chips being positioned in a stacked orientation with respect to each other;    electrically interconnecting at least one selected contact of first and second sets of contacts using the support structure;    electrically connecting the at least one contact of the first and second set of contacts to a mounting pad on a substrate such that the electrically interconnected at least one contact receives a conmmon signal;    forming an isolated pathway from at least one other of the first set of contacts to a mounting pad on the substrate; and    electrically connecting at least one other contact from the first set of contacts to a mounting pad formed on the substrate using the isolated pathway so that the at least one other contact is electrically isolated from the second set of contacts such that the at least one other contact receives an individual signal.    
     
     
         10 . The method of  claim 9 , wherein attaching the first set of contacts and attaching the second set of contacts comprises attaching the first set of contacts to an upper surface of the support structure and attaching the second set of contacts to a lower surface of the support structure so that the contacts are separated by the thickness of the support structure.  
     
     
         11 . The method of  claim 10 , wherein electrically interconnecting the at least one selected contact of the first and second sets of contacts using the support structure comprises: 
 forming a via that extends between the first and second surface of the support structure;    electrically interconnecting the at least one selected contacts of the first and second set of contacts using the via.    
     
     
         12 . The method of  claim 10 , wherein forming an isolated pathway comprises: 
 forming a via that extends through the support structure;    positioning a conductor within the via; and    connecting the conductor within the via to the at least one other contact from the first set of contacts and to the mounting pad on the substrate.    
     
     
         13 . The method of  claim 10  further comprising: 
 attaching a third set of contacts of a third chip to a third set of mounting pads formed on a third surface of a second support structure;  
 attaching the first set of contacts of the first chip to a fourth set of mounting pads formed on a fourth surface of the second support structure, wherein attaching the first and third sets of contacts to the second support structure results in the first, second, and third chips being positioned in a stacked orientation with respect to each other;  
 electrically interconnecting at least one selected contact of first and third sets of contacts using the second support structure;  
 electrically interconnecting at least one selected contact of the second set of contacts and the at least one selected contact of the first set of contacts;  
 electrically connecting the at least one selected contact of the first, second and third sets of contacts to a mounting pad on a substrate such that the electrically interconnected at least one selected contact receives a common signal;  
 forming an isolated pathway from at least one other of the third set of contacts to a mounting pad on the substrate; and  
 electrically connecting at least one other contact from the third set of contacts to a mounting pad formed on the substrate using the isolated pathway so that the at least one other contact is electrically isolated from the first and second sets of contacts such that the at least one other contact from the third set of contacts receives an individual signal.  
 
     
     
         14 . A chip stack for mounting on a substrate having a plurality of contact pads comprising at least a first and a second chip and a conducting interconnecting means for interconnecting the chips and maintaining the chips in a stacked configuration so that the chips are interconnected with at least one contact on the first and second chips being electrically interconnected and wherein the interconnecting means interconnects the at least one of the contacts of the first chip to a contact pad on the substrate in a manner that isolates the contact of the first chip from the contacts of the second chip.  
     
     
         15 . The chip stack of  claim 14 , wherein the interconnecting means comprises a support structure having a first and a second side wherein the first side is positioned proximate the substrate to permit electrical connection between the support structure and the substrate and wherein the second side is substantially parallel to the first side.  
     
     
         16 . The chip stack of  claim 15 , wherein the support structure includes a plurality of vias extending between the first and second side wherein at least one via extends between the first and second side to permit electrical connection of the at least one contact of the first chip to the contact pad on the substrate in a manner that isolates the contact of the first chip from the contacts of the second chip.  
     
     
         17 . The chip stack of  claim 16 , wherein the at least one of the vias extends to permit electrical interconnection between the at least one contacts on the first and second chip.  
     
     
         18 . A chip stack of at least one preformed support structure interconnecting a first chip to a second chip wherein the support structure comprises: 
 a member having a first surface and a second surface;    a plurality of surface mount pads disposed along the first surface and the second surface of the member;    a plurality of vias disposed between the first surface and the second surface of the member; and    a plurality of conducting elements wherein the conducting elements interconnect the surface mount pads and the vias.    
     
     
         19 . The member of  claim 18  wherein the first and second surfaces are substantially parallel to each other.  
     
     
         20 . The chip stack of  claim 18  wherein the at least one preformed support structure comprises a plurality of support structures.  
     
     
         21 . The chip stack of  claim 18  wherein the first chip and the second chip comprise memory chips.  
     
     
         22 . The chip stack of  claim 18  wherein the member is a printed circuit board.  
     
     
         23 . A chip stack module comprising: 
 a first chip comprising a first set of common contacts and a first set of individual contacts;    a second chip comprising a second set of common contacts and a second set of individual contacts; and    an interconnecting structure wherein the interconnecting structure further includes at least one interconnect and at least one via connection whereby the interconnecting structure interconnects the first and second chips wherein the first set of common contacts is electrically connected to the second set of common contacts and the first set of individual contacts and does not electrically connect to the second set of individual contacts, the first set of common contacts, and the second set of common contacts.    
     
     
         24 . The chip stack module of  claim 23  wherein the first and second chips are memory chips.  
     
     
         25 . The chip stack module of  claim 23  wherein the first and second chips are functionally identical.  
     
     
         26 . The chip stack module of  claim 23  wherein the first set of individual contacts and the second set of common contacts of the second chip are conductively connected to a printed circuit board.  
     
     
         27 . The chip stack module of  claim 23  wherein the interconnecting structure is a printed circuit board.  
     
     
         28 . The chip stack module of  claim 23 , wherein interconnecting structure provides a support surface so as to maintain the first and second chips in a stacked configuration and wherein the support surface defines a first and second surface with the contacts of the first chip being connected to the first surface and the contacts of the second chip being connected to the second surface.  
     
     
         29 . The chip stack module of  claim 28 , wherein the interconnecting structure comprises a plurality of vias that extend from the first surface to the second surface wherein a first set of vias interconnect common contacts and a second set of vias provide for isolated electrical connection of the first set of individual contacts to a structure located adjacent the second side of the interconnecting structure.  
     
     
         30 . A chip stack comprising: 
 a first chip having a generally planar formed top surface and first set of contacts formed in a first pattern comprising a first set of signals and a second set of signals;    a second chip having the generally planar formed top surface and a second set of contacts formed in the first pattern comprising a third set of signals and a fourth set of signals;    a support structure having a first side and a second side comprising: 
 a first set of surface mount pads on the first side;  
 a second set of surface mount pads on the second side;  
 a plurality of conducting elements;  
 a plurality of vias positioned through the support structure from the first side to the second side and spaced from the conducting elements;  
 whereby the conducting elements electrically interconnect the first and third sets of contacts, and the vias electrically conduct the fourth set of contacts without interconnecting the fourth set of contacts to the first, second and third sets of contacts, when the support structure is positioned between stacked first and second chips.  
   
     
     
         31 . The chip stack of  claim 30  further comprising a second support structure and a third chip.  
     
     
         32 . The first chip and the second chip of  claim 30  further comprising memory chips.  
     
     
         33 . The chip stack of  claim 30  wherein the first set of surface mount pads are conductively connected to a plurality of surface mount pads of a printed wiring board.