Spacer for semiconductor devices, semiconductor devices and assemblies including the spacer, and methods

Abstract

A semiconductor device that includes at least one nonconfluent spacer layer on at least one surface thereof. The at least one nonconfluent spacer layer at least partially spaces the surface of the semiconductor device apart from another semiconductor device assembled in stacked arrangement therewith. Adjacent stacked semiconductor devices may include abutting nonconfluent spacer layers which together define a distance between opposed surfaces of the semiconductor devices. Each nonconfluent spacer layer includes voids therein that communicate with an exterior periphery of the layer to facilitate the lateral introduction of adhesive or encapsulant material into the layer and between the adjacent, stacked semiconductor devices. Multi-chip modules are also disclosed, as are methods for forming the nonconfluent spacer layers and assembly and packaging methods.

What is claimed is:  
     
         1 . A method for preparing a semiconductor device to be used in a multi-chip module, comprising: 
 providing at least one semiconductor device; and    forming at least one nonconfluent spacer layer on at least one surface of said at least one semiconductor device.    
     
     
         2 . The method of  claim 1 , wherein said forming comprises forming nonconfluent spacer layers on both surfaces of said at least one semiconductor device.  
     
     
         3 . The method of  claim 1 , wherein said forming comprises screen printing.  
     
     
         4 . The method of  claim 1 , wherein said forming comprises: 
 forming a material layer on said at least one surface; and    patterning said material layer.    
     
     
         5 . The method of  claim 4 , wherein said forming said material layer comprises 
 depositing said material layer.    
     
     
         6 . The method of  claim 4 , wherein said patterning comprises: 
 forming a mask over said material layer; and    removing portions of said material layer exposed through said mask.    
     
     
         7 . The method of  claim 1 , wherein said forming comprises stereolithographically forming said at least one nonconfluent spacer layer.  
     
     
         8 . The method of  claim 7 , wherein said stereolithographically forming comprises: 
 forming a layer comprising unconsolidated material over said at least one surface; and    at least partially consolidating selected portions of said layer.    
     
     
         9 . The method of  claim 8 , further comprising: 
 forming at least one additional layer comprising unconsolidated material over said layer; and    at least partially consolidating selected portions of said at least one additional layer, said at least partially consolidated portions of said another layer being at least partially superimposed over, contiguous with, and adhered to said at least partially consolidated portions of said layer.    
     
     
         10 . The method of  claim 9 , further comprising: 
 repeating said forming and said at least partially consolidating at least once.    
     
     
         11 . A method for designing a semiconductor device to be used in a stacked multi-chip module, comprising: 
 configuring at least one nonconfluent spacer layer to be positioned on at least one surface of the semiconductor device.    
     
     
         12 . The method of  claim 11 , wherein said configuring comprises configuring said at least one nonconfluent spacer layer with at least one void to facilitate lateral introduction of adhesive material through said at least one nonconfluent spacer layer onto said at least one surface of the semiconductor device.  
     
     
         13 . The method of  claim 11 , wherein said configuring comprises configuring said at least one nonconfluent spacer layer to have a thickness that exceeds a distance at least one discrete conductive element will protrude above a surface of at least one of the semiconductor device and another, adjacent semiconductor device of the multi-chip module.  
     
     
         14 . The method of  claim 11 , wherein said configuring comprises configuring said at least one nonconfluent spacer layer to have a thickness that is about the same as or less than a distance at least one discrete conductive element will protrude above a surface of at least one of the semiconductor device and another, adjacent semiconductor device of the multi-chip module.  
     
     
         15 . The method of  claim 11 , wherein said configuring comprises configuring said at least one nonconfluent spacer layer to include a plurality of laterally discrete spacers.  
     
     
         16 . The method of  claim 11 , wherein said configuring comprises configuring said at least one nonconfluent spacer layer to be positioned adjacent another spacer layer, said at least one nonconfluent spacer layer and said another spacer layer together defining a distance the semiconductor device is to be spaced apart from another, adjacent semiconductor device of the multi-chip module.  
     
     
         17 . A method for forming a stacked assembly of semiconductor devices, comprising: 
 providing a first semiconductor device;    applying a nonconfluent spacer layer to at least one surface of said first semiconductor device; and    positioning a second semiconductor device in stacked arrangement relative to said first semiconductor device, said nonconfluent spacer layer at least partially spacing said first and second semiconductor devices apart from one another.    
     
     
         18 . The method of  claim 17 , further comprising: 
 securing said first semiconductor device and a substrate to one another.    
     
     
         19 . The method of  claim 18 , wherein said securing comprises securing a back side of 
 said first semiconductor device to said substrate.    
     
     
         20 . The method of  claim 18 , wherein said securing comprises securing said substrate to portions of an active surface of said first semiconductor device.  
     
     
         21 . The method of  claim 18 , further comprising: 
 electrically connecting at least one bond pad of said first semiconductor device to a corresponding contact area of said substrate.    
     
     
         22 . The method of  claim 21 , wherein said electrically connecting comprises: 
 positioning or forming a discrete conductive element between said at least one bond pad and said corresponding contact area.    
     
     
         23 . The method of  claim 21 , wherein said electrically connecting comprises placing a lead at least partially over said at least one bond pad.  
     
     
         24 . The method of  claim 18 , wherein said applying is effected before said securing.  
     
     
         25 . The method of  claim 18 , wherein said applying is effected after said securing.  
     
     
         26 . The method of  claim 21 , wherein said applying is effected after said electrically connecting.  
     
     
         27 . The method of  claim 17 , further comprising: 
 applying another nonconfluent spacer layer to at least one surface of said second semiconductor device.    
     
     
         28 . The method of  claim 27 , wherein, upon said positioning, said nonconfluent spacer layer and said another nonconfluent spacer layer are positioned against one another.  
     
     
         29 . The method of  claim 17 , wherein, upon said positioning, said nonconfluent spacer layer adheres said first and second semiconductor devices to one another.  
     
     
         30 . The method of  claim 17 , further comprising: 
 laterally introducing adhesive material into voids in said nonconfluent spacer layer and between said first and second semiconductor devices.    
     
     
         31 . The method of  claim 30 , further comprising at least one of at least partially curing and at least partially hardening said adhesive material.  
     
     
         32 . The method of  claim 21 , further comprising: 
 electrically connecting at least one bond pad of said second semiconductor device to another corresponding contact area of said substrate.    
     
     
         33 . The method of  claim 32 , further comprising: 
 encapsulating at least portions of said first semiconductor device, said second semiconductor device, and said substrate.    
     
     
         34 . The method of  claim 33 , wherein said encapsulating comprises forming a molded encapsulant.  
     
     
         35 . The method of  claim 33 , wherein said encapsulating comprises forming a glob-top encapsulant.