Matrix display apparatus, matrix display control apparatus, and matrix display drive apparatus

Abstract

A matrix-type display control device suited to large capacity displays while achieving low power consumption operation is achieved by improving the display data transfer method. The module controller 100 of a simple matrix-type liquid crystal display comprises a low frequency oscillator 110, timing signal generator 120, standby circuit (display data refresh detection circuit) 130, high frequency oscillator 140, and a direct memory access (DMA circuit) 150. This low frequency oscillator 110 constantly generates the low frequency clock f L . Timing signal generator 120 generates the scan start signal YD required for the LCD module 200, and other signals based on the low frequency clock f L . Standby circuit 130 generates the intermittent operation start control signal {overscore (ST)} when the display data in VRAM 12 is updated as determined by monitoring the system bus 14 a for communications with host MPU 10. The high frequency oscillator 140 generates the high frequency clock f H phase synchronized to the low frequency clock f L during the intermittent operation start control signal {overscore (ST)} apply period. The DMA circuit 150 reads the display data from the VRAM 12 over dedicated bus 14 b by direct memory access, and transfers the display data over data bus 17 to the frame memories 252 - 1˜252 -N of X drivers 250 - 1˜250 -N during the intermittent operation start control signal {overscore (ST)} apply time using the high frequency clock f H .

What is claimed is:  
     
         1 . A matrix display control apparatus comprising: 
 a matrix display device of display elements arranged in a matrix pattern, having signal electrodes;    a first memory for storing a plurality of display data;    a second memory for storing a subset of said display data;    a signal electrode drive means for applying a drive voltage to said signal electrodes according to said display data read from said second memory; and    a display data transfer means for reading the display data associated with the change from the first RAM device according to the high frequency clock output from the intermittent high frequency oscillator, and transferring the read display data together with the high frequency clock to the second RAM device;    and characterized by an intermittent high frequency oscillator that oscillates according to changes in the display data stored in the first RAM device.    
     
     
         2 . The matrix display control apparatus comprising: 
 an intermittently operating high frequency oscillator that oscillates according to changes in the display data stored in a first RAM device, and    a display data transfer means for reading the display data associated with the change from said first RAM device according to the high frequency clock output from the intermittent high frequency oscillator, and transferring the read display data together with the high frequency clock to the second RAM device.    
     
     
         3 . A matrix display control apparatus comprising: 
 a low frequency oscillator for constantly generating a low frequency clock,    a timing signal generator for generating a specified timing signal based on the low frequency clock from the low frequency oscillator,    a display data refresh detection means for generating an intermittent control signal based on changes in the display data stored in the first RAM device,    an intermittent high frequency oscillator that oscillates according to the intermittent control signal,    and a display data transfer means for reading the display data associated with the change from the first RAM device according to the high frequency clock output from the intermittent high frequency oscillator, and transferring the read display data together with the high frequency clock to the second RAM device.    
     
     
         4 . A matrix display drive apparatus comprising a second random access memory device for storing the display data of at least part of the display elements, 
 reading the display data from the second RAM device,    and applying a drive voltage to the signal electrodes of the matrix display device,    and characterized by a timing signal generator for generating a write control signal and a read control signal at an offset timing within one scanning period based on the cycle signal received each scanning period,    and a read/write means for executing a read operation according to the read control signal and then executing a write operation according to the write control signal with both operations addressing the same address in the second RAM device.    
     
     
         5 . The apparatus of  claim 4  further comprising a clock detection means for detecting when the high frequency clock used for display data transfer stops; 
 and a write prohibit control means for preventing generation of the write control signal based on this detection signal.  
 
     
     
         6 . The apparatus of  claim 5  wherein the read/write means comprises a temporary storage means for sequentially storing at least one scan line of the incoming display data using the high frequency clock; 
 and a buffer for writing to the second RAM device the stored display data from the temporary storage means according to a signal longer than one cycle of the high frequency clock.  
 
     
     
         7 . The apparatus of  claim 4  wherein the read/write means comprises a signal voltage state assignment means for extracting the signal voltage to be applied to the signal electrode from the display data read from the second RAM device and the voltage state of the scanning electrode of the matrix display device.  
     
     
         8 . The apparatus of  claim 7  wherein the signal voltage state assignment means comprises a means for reading plural scan lines of display data from the second RAM device on a time-share basis; 
 a temporary storage means that alternately waits for the read display data,  
 a scan state setting means for specifying the voltage state of the scan electrode of the matrix display device;  
 and a voltage selector for selecting the drive voltage from the plural scan line display data read from the second RAM device and the selected voltage state of the scan electrode.  
 
     
     
         9 . The apparatus of  claim 7  wherein the second RAM device comprises a memory array for storing plural scan lines of display data for one line address of the matrix display device; 
 and the signal voltage state assignment means comprises a means for batch reading plural scan lines of display data;  
 a scan state setting means for specifying the voltage state of the scan electrode of the matrix display device;  
 and a voltage selector for selecting the drive voltage from the plural scan line display data read from the second RAM device and the selected voltage state of the scan electrode.  
 
     
     
         10 . A matrix display drive apparatus that drives a selected scan electrode of the matrix display device; 
 and comprises a means for simultaneously selecting and cyclically scanning plural scan electrodes plural times within the period of the frame start signal.    
     
     
         11 . A matrix display control apparatus comprising: 
 a) a matrix display device having display elements arranged in a matrix pattern, and having signal electrodes;    b) a first memory for storing display data;    c) a second memory, coupled to said first memory, that stores a subset of said display data;    d) an intermittent high frequency oscillator, coupled to said first memory, that oscillates according to changes in the display data stored in said first memory;    e) a signal electrode drive means, coupled to said signal electrodes, for applying a drive voltage to said signal electrodes according to said display data read from said second memory; and    f) a display data transfer means for reading a portion of said display data from said first memory according to an output of said intermittent high frequency oscillator, and transferring said portion of said display data together with said output of said intermittent high frequency oscillator to said second memory.    
     
     
         12 . The apparatus of  claim 11  further comprising: 
 a) a low frequency oscillator for generating a low frequency clock;  
 b) a timing signal generator, coupled to said low frequency oscillator, for generating a predetermined timing signal from said low frequency clock; and  
 c) a display data update detection means, coupled to said first memory, for generating a control signal based on changes to said display data stored in said first memory.