Data processing system with improved latency and associated methods

Abstract

An configurable integrated-circuit device includes a plurality of regions that each contain electronic circuitry. The configurable integrated-circuit device also includes common circuitry adapted to provide at least one signal to at least two regions of the plurality of regions. The common circuitry and the at least two regions are positioned within the configurable integrated-circuit device so as to improve the latencies of the at least one signal to each of the at least two regions.

I claim:  
     
         1 . A configurable integrated-circuit device, comprising: 
 a plurality of regions that each include configurable electronic circuitry; and    common circuitry that provides at least one signal to at least two regions of the plurality of regions,    wherein the common circuitry and the at least two regions are positioned within the configurable integrated-circuit device so as to improve the latencies of the at least one signal to each of the at least two regions.    
     
     
         2 . The configurable integrated-circuit device of  claim 1 , in which the common circuitry comprises at least one processor circuitry.  
     
     
         3 . The configurable integrated-circuit device of  claim 2 , in which the common circuitry further comprises at least one memory circuitry that communicates with the at least one processor circuitry.  
     
     
         4 . The configurable integrated-circuit device of  claim 3 , further comprising at least one bus circuitry that couples the common circuitry to the plurality of regions within the configurable integrated-circuit device.  
     
     
         5 . The configurable integrated-circuit device of  claim 4 , in which the common circuitry further comprises a clock generator circuitry that provides at least one clock signal.  
     
     
         6 . The configurable integrated-circuit device of  claim 5 , further comprising at least one port circuitry that facilitates communication between the at least two regions.  
     
     
         7 . The configurable integrated-circuit device of  claim 6 , further comprising at least one dual-port memory circuitry coupled to the at least two regions.  
     
     
         8 . The configurable integrated-circuit device of  claim 7 , further comprising input/output (IO) circuitry that facilitates communication between the common circuitry and circuitry external to the configurable integrated-circuit device.  
     
     
         9 . The configurable integrated-circuit device of  claim 8 , in which the common circuitry is positioned at substantially the same distance from each region of the plurality of regions.  
     
     
         10 . The configurable integrated-circuit device of  claim 8 , in which the common circuitry is positioned at substantially the same distance from each of the at least two regions of the plurality of regions.  
     
     
         11 . A data-processing system including a configurable integrated-circuit device according to  claim 1 , the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.  
     
     
         12 . A data-processing system including a configurable integrated-circuit device according to  claim 2 , the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.  
     
     
         13 . A data-processing system including a configurable integrated-circuit device according to  claim 3 , the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.  
     
     
         14 . A data-processing system including a configurable integrated-circuit device according to  claim 4 , the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.  
     
     
         15 . A data-processing system including a configurable integrated-circuit device according to  claim 5 , the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.  
     
     
         16 . A configurable integrated-circuit device, comprising: 
 a plurality of regions that each include configurable electronic circuitry; and    common circuitry that provides at least one signal to at least two regions of the plurality of regions,    wherein the common circuitry and the at least two regions are positioned within the configurable integrated-circuit device so that the latencies of the at least one signal to each of the at least two regions tend to be equalized.    
     
     
         17 . The configurable integrated-circuit device of  claim 16 , in which the common circuitry comprises at least one processor circuitry.  
     
     
         18 . The configurable integrated-circuit device of  claim 17 , in which the common circuitry further comprises at least one memory circuitry that communicates with the at least one processor circuitry.  
     
     
         19 . The configurable integrated-circuit device of  claim 18 , further comprising at least one bus circuitry that couples the common circuitry to the plurality of regions within the configurable integrated-circuit device.  
     
     
         20 . The configurable integrated-circuit device of  claim 19 , in which the common circuitry further comprises a clock generator circuitry that provides at least one clock signal.  
     
     
         21 . The configurable integrated-circuit device of  claim 20 , further comprising at least one port circuitry that facilitates communication between the at least two regions.  
     
     
         22 . The configurable integrated-circuit device of  claim 21 , further comprising at least one dual-port memory circuitry coupled to the at least two regions.  
     
     
         23 . The configurable integrated-circuit device of  claim 22 , further comprising input/output (IO) circuitry that facilitates communication between the common circuitry and circuitry external to the configurable integrated-circuit device.  
     
     
         24 . The configurable integrated-circuit device of  claim 23 , in which the common circuitry is positioned centrally with respect to the plurality of regions.  
     
     
         25 . The configurable integrated-circuit device of  claim 23 , in which the common circuitry is positioned centrally with respect to the at least two regions of the plurality of regions.  
     
     
         26 . A data-processing system including a configurable integrated-circuit device according to  claim 16 , the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.  
     
     
         27 . A data-processing system including a configurable integrated-circuit device according to  claim 17 , the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.  
     
     
         28 . A data-processing system including a configurable integrated-circuit device according to  claim 18 , the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.  
     
     
         29 . A data-processing system including a configurable integrated-circuit device according to  claim 19 , the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.  
     
     
         30 . A data-processing system including a configurable integrated-circuit device according to  claim 20 , the data-processing system further comprising at least one peripheral circuitry coupled to the configurable integrated-circuit device.  
     
     
         31 . A programmable logic device, comprising: 
 a plurality of regions that each include configurable electronic circuitry;    bus circuitry coupled to the plurality of regions; and    common circuitry coupled to the bus circuitry,    wherein the common circuitry provides a signal to the plurality of regions through the bus circuitry, and    wherein the common circuitry and the plurality of regions are positioned within the programmable logic device so as to improve the latencies of the signal to each region.    
     
     
         32 . The programmable logic-device of  claim 31 , in which the common circuitry comprises at least one processor circuitry.  
     
     
         33 . The programmable logic-device of  claim 32 , in which the common circuitry further comprises at least one memory circuitry configured to communicate with the at least one processor circuitry.  
     
     
         34 . The programmable logic-device of  claim 33 , further comprising configurable interconnect circuitry coupled to each region.  
     
     
         35 . The programmable logic-device of  claim 34 , further comprising input-output (I/O) circuitry coupled to the common circuitry.  
     
     
         36 . The programmable logic-device of  claim 35 , in which the input-output circuitry is further coupled to the plurality of regions.  
     
     
         37 . The programmable logic-device of  claim 36 , further comprising a memory controller circuitry adapted to communicate with memory circuitry external to the programmable logic-device.  
     
     
         38 . The programmable logic-device of  claim 37 , in which the common circuitry further comprises a dual-port memory circuitry adapted to facilitate communication between a plurality of processor circuitries within the common circuitry.  
     
     
         39 . The programmable logic-device of  claim 38 , which includes four regions, each region positioned in a quadrant of the programmable logic-device.  
     
     
         40 . The programmable logic-device of  claim 39 , in which the bus circuitry includes a horizontal bus circuitry and a vertical bus circuitry that intersects the horizontal bus circuitry, wherein the intersection of the horizontal bus circuitry and the vertical bus circuitry overlaps at least in part with the common circuitry.  
     
     
         41 . A data-processing system including a programmable logic-device according to  claim 31 , the data-processing system further comprising at least one peripheral circuitry coupled to the programmable logic-device.  
     
     
         42 . A data-processing system including a programmable logic-device according to  claim 32 , the data-processing system further comprising at least one peripheral circuitry coupled to the programmable logic-device.  
     
     
         43 . A data-processing system including a programmable logic-device according to  claim 33 , the data-processing system further comprising at least one peripheral circuitry coupled to the programmable logic-device.  
     
     
         44 . A data-processing system including a programmable logic-device according to  claim 34 , the data-processing system further comprising at least one peripheral circuitry coupled to the programmable logic-device.  
     
     
         45 . A data-processing system including a programmable logic-device according to  claim 35 , the data-processing system further comprising at least one peripheral circuitry coupled to the programmable logic-device.  
     
     
         46 . A data-processing system including a programmable logic-device according to  claim 36 , the data-processing system further comprising at least one peripheral circuitry coupled to the programmable logic-device.  
     
     
         47 . A method of improving latency in a configurable integrated-circuit device, comprising: 
 providing the configurable integrated-circuit device;    partitioning the configurable integrated-circuit device into a plurality of regions that each include configurable electronic circuitry;    including within configurable the integrated-circuit device a common circuitry that provides at least one signal to at least two regions of the plurality of regions; and    positioning the common circuitry and the at least two regions within the configurable integrated-circuit device so as to improve the latencies of the at least one signal to each of the at least two regions.    
     
     
         48 . The method of  claim 47 , which further comprises including in the common circuitry at least one processor circuitry.  
     
     
         49 . The method of  claim 48 , which further comprises including in the common circuitry at least one memory circuitry configured to communicate with the at least one processor circuitry.  
     
     
         50 . The method of  claim 49 , which further comprises including in the configurable integrated-circuit device at least one bus circuitry adapted to couple the common circuitry to the plurality of regions of the integrated-circuit device.  
     
     
         51 . The method of  claim 50 , which further comprises including in the common circuitry a clock generator circuitry adapted to provide at least one clock signal.  
     
     
         52 . The method of  claim 51 , which further comprises including in the integrated-circuit device at least one port circuitry adapted to facilitate communication between the at least two regions.  
     
     
         53 . The method of  claim 52 , which further comprises including in the integrated-circuit device at least one dual-port memory circuitry coupled to the at least two regions.  
     
     
         54 . The method of  claim 53 , which further comprises including in the integrated-circuit device at least one dedicated input/output (IO) circuitry adapted to facilitate communication between the common circuitry and circuitry external to the integrated-circuit device.  
     
     
         55 . The method of  claim 54 , which further comprises positioning the common circuitry at substantially the same distance from each region of the plurality of regions.  
     
     
         56 . The method of  claim 54 , which further comprises positioning the common circuitry at substantially the same distance from each of the at least two regions of the plurality of regions.  
     
     
         57 . A method of improving latency in a configurable integrated-circuit device, comprising: 
 providing the configurable integrated-circuit device;    partitioning the configurable integrated-circuit device into a plurality of regions that each include configurable electronic circuitry;    including within the configurable integrated-circuit device a common circuitry that provides at least one signal to at least two regions of the plurality of regions; and    positioning the common circuitry and the at least two regions within the configurable integrated-circuit device so that the latencies of the at least one signal to each of the at least two regions tend to be equalized.    
     
     
         58 . The method of  claim 57 , which further comprises including in the common circuitry at least one processor circuitry.  
     
     
         59 . The method of  claim 58 , which further comprises including in the common circuitry at least one memory circuitry configured to communicate with the at least one processor circuitry.  
     
     
         60 . The method of  claim 59 , which further comprises including in the configurable integrated-circuit device at least one bus circuitry adapted to couple the common circuitry to the plurality of regions of the integrated-circuit device.  
     
     
         61 . The method of  claim 60 , which further comprises including in the common circuitry a clock generator circuitry adapted to provide at least one clock signal.  
     
     
         62 . The method of  claim 61 , which further comprises including in the integrated-circuit device at least one port circuitry adapted to facilitate communication between the at least two regions.  
     
     
         63 . The method of  claim 62 , which further comprises including in the integrated-circuit device at least one dual-port memory circuitry coupled to the at least two regions.  
     
     
         64 . The method of  claim 63 , which further comprises including in the integrated-circuit device at least one dedicated input/output (IO) circuitry adapted to facilitate communication between the common circuitry and circuitry external to the integrated-circuit device.  
     
     
         65 . The method of  claim 64 , which further comprises positioning the common circuitry at substantially the same distance from each region of the plurality of regions.  
     
     
         66 . The method of  claim 64 , which further comprises positioning the common circuitry at substantially the same distance from each of the at least two regions of the plurality of regions.