Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device, which enables impedance adjustment of a particular pad without affecting other pads or signal wirings or without the need for a design change in basic layout, has formed a number of elements and wirings on and in a silicon substrate 11 , and pads 13 stacked thereon via an insulation film 12 . A particular pad 13 a is connected to a signal wiring 17 a formed in a bus line region 17 , and a capacitor-forming conductor 14 behaving as an impedance adjusting conductor is formed to surround the pad 13 a. A source line conductor 15 is made in a space between the pad 13 a and the capacitor-forming conductor 14 to encircle the capacitor-forming conductor 14 . Therefore, the pad capacitance can be increased by using the space around the pad 13 a, other signal wirings 17 b and any others formed in the bus line region 17 are not affected substantially. Since here is used the portion around the pad which is not used normally, the basic layout need not be changed.

What is claimed is:  
     
         1 . A semiconductor integrated circuit device including semiconductor elements, signal wirings and pads each formed on a semiconductor substrate so as to connect particular one of said semiconductor elements to particular one of said signal wirings and to connect said particular signal wiring to particular one of said pads, comprising: 
 a capacitor-forming conductor made in a top layer, arranged around said particular pad to surround said particular pad and connected to said particular pad; and    a first capacitance coupling conductor made in the top layer between said particular pad and said capacitor-forming conductor and brought into capacitance coupling with said particular pad and said capacitor-forming conductor, respectively.    
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , which further comprising a second capacitance-coupling conductor made in the top layer outside said capacitor-forming conductor and brought into capacitance coupling with said capacitor-forming conductor.  
     
     
         3 . The semiconductor integrated circuit device according to  claim 2 , wherein said first and second capacitance-coupling conductors are connected to each other.  
     
     
         4 . The semiconductor integrated circuit device according to  claim 2 , wherein said first and second capacitance-coupling conductors are connected to a power source line of a lower voltage.  
     
     
         5 . The semiconductor integrated circuit device according to  claim 1 , which has a multi-layered structure including a first layer as the bottom layer, an Nth layer as the top layer, and an insulation film between every two vertically adjacent layers, said Nth layer including said capacitor-forming conductor of the top layer and said first capacitance-coupling conductor of the top layer, each of (N−1)th to first layers having said capacitor-forming conductor for a lower layer and said first capacitance-coupling conductor for the lower layer, every two said layers vertically adjacent to each other having patterns of said capacitor-forming conductors and said first capacitance-coupling conductors inverted from each other so as to confront the pattern of said capacitor-forming conductor of a Pth layer with said capacitance-coupling conductor of a (P−1)th layer vertically adjacent to said Pth layer via said insulation film and to confront said capacitance-coupling conductor of the Pth layer with said capacitor-forming conductor of the (P−1)th layer via said insulation film, said capacitor-forming conductors of vertically adjacent two of said layers being connected to each other, and said capacitance-coupling conductors of vertically adjacent two of said layers being connected to each other.  
     
     
         6 . The semiconductor integrated circuit device according to  claim 2 , which has a multi-layered structure including a first layer as the bottom layer, an Nth layer as the top layer, and an insulation film between every two vertically adjacent layers, said Nth layer including said capacitor-forming conductor of the top layer and said first and second capacitance-coupling conductors of the top layer, each of (N−1)th to first layers having said capacitor-forming conductor for a lower layer and said first and second capacitance-coupling conductors for the lower layer, every two said layers vertically adjacent to each other having patterns of said capacitor-forming conductors and said capacitance-coupling conductors inverted from each other so as to confront the pattern of said capacitor-forming conductor of a Pth layer with said capacitance-coupling conductors of a (P−1)th layer vertically adjacent to said Pth layer via said insulation film and to confront said capacitance-coupling conductors of the Pth layer with said capacitor-forming conductor of the (P−1)th layer via said insulation film, said capacitor-forming conductors of vertically adjacent two of said layers being connected to each other, and said capacitance-coupling conductors of vertically adjacent two of said layers being connected to each other.  
     
     
         7 . A semiconductor integrated circuit device comprising: 
 semiconductor elements, signal wirings and pads each formed on a semiconductor substrate so as to connect particular one of said semiconductor elements to particular one of said signal wirings and to connect said particular signal wiring to particular one of said pads; and    a resistor-forming conductor connected between said particular signal wiring and said particular pad.    
     
     
         8 . The semiconductor integrated circuit device according to  claim 7 , wherein said resistor-forming conductor is located around said particular pad.  
     
     
         9 . The semiconductor integrated circuit device according to  claim 8 , wherein said resistor-forming conductor has a spiral pattern.  
     
     
         10 . The semiconductor integrated circuit device according to  claim 7 , wherein said particular pad formed on upper layer whereas said resistor-forming, conductor formed on a lower layer under said upper layer confronting with said upper layer via an insulation film, said particular pad and said resistor-forming conductor being connected by a contact passing through said insulation film.  
     
     
         11 . The semiconductor integrated circuit device according to  claim 10 , wherein said resistor-forming conductor includes resistor-forming conductor units each made on each of a plurality of layers, and selective ones of said resistor-forming conductor units are connected to adjust the resistance value.  
     
     
         12 . The semiconductor integrated circuit device according to  claim 9 , wherein a capacitance-coupling conductor is made between said particular pad and said resistor-forming conductor having the spiral pattern and brought into capacitance coupling with said particular pad and said resistor-forming conductor.  
     
     
         13 . A semiconductor integrated circuit device comprising: 
 semiconductor elements, signal wirings and pads each formed on a semiconductor substrate so as to connect particular one of said semiconductor elements to particular one of said signal wirings and to connect said particular signal wiring to particular one of said pads;    a first capacitance-coupling conductor made under said particular pad via an insulation film;    a capacitor-forming conductor made under said capacitance-coupling conductor via an insulation film and connected to said particular pad; and    a second capacitance-coupling conductor made under said capacitor-forming conductor via an insulation film and connected to said first capacitance-coupling conductor.    
     
     
         14 . A semiconductor integrated circuit device comprising a semiconductor substrate having a plurality of elements, signal wirings connecting these elements, a plurality of pads for connecting desired one or more of the signal wirings to one on more external pins formed on said semiconductor substrate, and 
 at least one impedance adjusting conductor pattern made to surround particular one of said pads and connected to said particular pad.    
     
     
         15 . The semiconductor integrated circuit device according to  claim 14 , wherein said impedance adjusting conductor pattern is a capacitor-forming conductor, and a power source line conductor is inserted in a space between said capacitor-forming conductor and said particular one of said pads, which power source line conductor being capacitance-coupled with said capacitor-forming conductor and said pad.  
     
     
         16 . The semiconductor integrated circuit device according to  claim 15 , wherein each of combination patterns of said power capacitor-forming conductor and said power source line conductor is made in each layer, said adjacent two of combination patterns being formed via each insulation layer, patterns of said capacitor-forming conductors and said source line conductors being inverted between adjacent layers, said capacitor-forming conductors of different layers being connected to each other, said source line conductors of different layers being connected to each other, and said capacitor-forming conductor of each layer being brought into capacitance coupling with said source line conductors of horizontally and vertically adjacent layers.  
     
     
         17 . The semiconductor integrated circuit device according to  claim 14 , wherein said impedance adjusting conductor pattern is a resistor-forming conductor inserted between particular one of said pads and said signal wiring connected thereto, and has a spiral shape surrounding said particular pad.  
     
     
         18 . The semiconductor integrated circuit device according to  claim 14 , which has a plurality of layers each having formed said impedance adjusting conductor pattern via an insulation film such that the value of impedance adjustment be controlled by making or not making contacts between said impedance adjusting conductor patterns in different layers.  
     
     
         19 . The semiconductor integrated circuit device according to  claim 14 , wherein said impedance adjusting conductor pattern extends into a prohibit region around the pad where wiring layout is prohibited from a design rule.