Silicide stop layer in a damascene semiconductor structure

Abstract

A damascene gate semiconductor structure that is formed utilizing a silicide stop layer. Initially, a gate opening is provided in an insulating layer on a substrate. A first dielectric layer is deposited in the gate opening over the substrate. A silicide stop layer is then deposited in the gate opening over the first silicon layer. A second silicon layer is then deposited in the gate opening over the silicide stop layer. A metal or alloy layer is then deposited over the insulating and the second silicon layer. The damascene semiconductor structure is then temperature treated to react the metal or alloy layer with the second silicon layer to form a silicide layer. Any unreated metal or alloy is then removed from the metal or alloy layer.

What is claimed is:  
     
         1 . A method of forming a damascene semiconductor structure, comprising the steps of: 
 providing a gate opening in an insulating layer on a substrate;    depositing a first silicon layer in the gate opening over the substrate;    depositing a silicide stop layer in the gate opening over the first silicon layer;    depositing a second silicon layer in the gate opening over the silicide stop layer;    depositing a metal or alloy layer over the insulating layer and the second silicon layer;    temperature treating the damascene semiconductor structure to react the metal or alloy layer with the second silicon layer to form a silicide layer; and    removing unreacted metal or alloy in the metal or alloy layer, the silicide stop layer preventing interaction of the first silicon layer with the metal or alloy layer.    
     
     
         2 . The method of  claim 1 , wherein the temperature treating is conducted between about 250° C. and about 750° C.  
     
     
         3 . The method of  claim 1 , wherein the silicide stop layer is about 10 Å to about 200 Å thick.  
     
     
         4 . The method of  claim 1 , wherein the silicide stop layer is conductive and comprises material that is a diffusion barrier during silicidation of the second silicon layer.  
     
     
         5 . The method of  claim 1 , wherein the silicide stop layer is comprised of one of SiN x , TiN x , WN x , WC x , and CrN x .  
     
     
         6 . The method of  claim 1 , wherein the metal layer is comprised of one of Ni, Ti, and Co.  
     
     
         7 . The method of  claim 1 , comprising the further step of depositing a dielectric layer in the gate opening over the substrate before the step of depositing the first silicon layer.  
     
     
         8 . The method of  claim 1 , wherein the dielectric layer is a gate dielectric.  
     
     
         9 . The method of  claim 1 , wherein the dielectric layer is comprised of a high k dielectric material.  
     
     
         10 . The method of  claim 1 , wherein the dielectric layer is comprised of an oxide dielectric.  
     
     
         11 . A damascene semiconductor structure comprising: 
 a dielectric layer on a substrate, the dielectric layer having a gate opening;    a gate dielectric in the gate opening and on the substrate;    a silicon layer on the gate dielectric;    a silicide stop layer on the silicon layer; and    a silicided layer on the silicide stop layer.    
     
     
         12 . The semiconductor structure of  claim 11 , wherein the silicide stop layer comprises a conductive material that is a diffusion barrier material.  
     
     
         13 . The semiconductor structure of  claim 11 , wherein the silicide stop layer is about 10 Å to about 200 Å thick.  
     
     
         14 . The semiconductor structure of  claim 11 , wherein the silicide stop layer is comprised of one of SiN x , TiN z , WN x , WC x , and CrN x .  
     
     
         15 . The semiconductor structure of  claim 11 , wherein the gate dielectric is comprised of an oxide dielectric.  
     
     
         16 . The semiconductor structure of  claim 11 , wherein the gate dielectric is comprised of a high k dielectric material.  
     
     
         17 . The semiconductor structure of  claim 11 , wherein the silicon layer is comprised of polycrystalline silicon material.  
     
     
         18 . The semiconductor structure of  claim 11 , wherein the silicide layer is comprised of one of SiN, SiTi, and SiCo.  
     
     
         19 . The semiconductor structure of  claim 11 , wherein the silicon layer is between about 200 Å and 500 Å thick.  
     
     
         20 . The semiconductor structure of  claim 11 , wherein the silicide layer is between about 600 Å and 1000 Å thick.