Endian transformation

Abstract

A method for emulating a processor of a first endian type on a processor of a second endian type, wherein each memory access address B of string length L is transformed to the address A−B−L+S, wherein A is the total number of bytes allocated to a program, and S is the start address of the program.

We claim:  
     
         1 . A method for emulating a processor of a first type which observes a first convention for ordering the significance of bytes within words on a second type of processor which observes a second convention for ordering the significance of bytes within words, wherein memory access addresses are transformed such that bytes stored in a memory addressed by a processor of the second type as a result of an instruction in which a byte order in accordance with the first convention is observed are distributed in a pattern which is a mirror image of the distribution pattern of the bytes which would result if the memory was addressed by a processor of the first type in response to the said instruction.  
     
     
         2 . A method for emulating a processor of a first type which observes a first convention for ordering the significance of bytes within words on a second type of processor which observes a second convention for ordering the significance of bytes within words, the order of the second convention being the reverse of the order of the first, wherein memory access addressed are transformed such that the offset between addresses of any two bytes stored in memory is unaltered by the transformation and the relative order of the addresses of any two bytes stored in the memory is reversed by the transformation.  
     
     
         3 . A method for emulating a processor of a first type which observes a first endian format for ordering the significance of bytes within words on a second type of processor which observes a second endian format for ordering the significance of bytes within words, wherein memory access addresses are transformed such that strings of bytes in the first endian format which are stored successively by the processor operating in accordance with the second endian format aggregate in the same manner as the bytes would aggregate if the processor was of the first endian format and memory access addresses were not transformed.  
     
     
         4 . A method for emulating a processor of a first type which observes a first convention for ordering the significance of bytes within words on a second type of processor which observes a second convention for ordering the significance of bytes within words, wherein each memory access address B of string length L is transformed to the address A−B−L+S, wherein A is the total number of bytes allocated to a program, and S is the start address of the program.  
     
     
         5 . A process for compiling or translating a computer program code instruction using transformed address space references in the compiled or translated code especially configured for execution on a programmable machine utilising a corresponding predetermined convention for ordering the significance of bytes within words of said address space, said process comprising: 
 (a) during compilation or translation of a code instruction referring to a memory address, transforming the referenced memory address with respect to a fixed block size of memory in the predetermined programmable machine so as to change the referenced address value by an amount that is fixed for a given number of bytes being accessed in each word; and    (b) including the thus changed address reference in a compiled or translated output instruction so that there is no extra operation required during execution of the output instruction to accommodate the convention for ordering bytes within words used by said predetermined programmable machine.    
     
     
         6 . A process according to  claim 5 , wherein said code is a computer program source code.  
     
     
         7 . A process according to  claim 5 , wherein said change causes said fixed block of memory to be addressed from a predetermined one of its two ends depending upon the convention utilised by said predetermined programmable machine for ordering the significance of bytes within words.  
     
     
         8 . A process according to  claim 5 , wherein said change causes the fixed block of memory contents for a big-endian machine to be inverted to the mirror image of that for a little-endian machine.  
     
     
         9 . An endian transformation system, comprising: 
 means for transforming a memory access address for use when a processor of a first type which observes a first convention for ordering the significance of bytes within words on a second type of processor which observes a second convention for ordering the significance of bytes within words, wherein memory access addresses are transformed such that bytes stored in a memory addressed by a processor of the second type as a result of an instruction in which a byte order in accordance with the first convention is observed are distributed in a pattern which is a mirror image of the distribution pattern of the bytes which would result if the memory was addressed by a processor of the first type in response to the said instruction.    
     
     
         10 . An endian transformation system, comprising: 
 means for transforming a memory access address for use when a processor of a first type which observes a first convention for ordering the significance of bytes within words on a second type of processor which observes a second convention for ordering the significance of bytes within words, the order of the second convention being the reverse of the order of the first, wherein memory access addressed are transformed such that the offset between addresses of any two bytes stored in memory is unaltered by the transformation and the relative order of the addresses of any two bytes stored in the memory is reversed by the transformation.    
     
     
         11 . An endian transformation system, comprising: 
 a processor of a first type which observes a first endian format for ordering the significance of bytes within words on a second type of processor which observes a second endian format for ordering the significance of bytes within words, wherein memory access addresses are transformed such that strings of bytes in the first endian format which are stored successively by the processor operating in accordance with the second endian format aggregate in the same manner as the bytes would aggregate if the processor was of the first endian format and memory access addresses were not transformed.    
     
     
         12 . An endian transformation system, comprising: 
 a processor of a first type which observes a first convention for ordering the significance of bytes within words on a second type of processor which observes a second convention for ordering the significance of bytes within words, wherein each memory access address B of string length L is transformed to the address A−B−L+S, wherein A is the total number of bytes allocated to a program, and S is the start address of the program.