Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface. The first and the second semiconductor chips are integrated so that the first and second main surfaces are opposed to one another and the first and second electrodes are electrically connected. The second semiconductor chip is polished from the opposite side of the second main surface so that the second semiconductor chip has a thickness smaller than the thickness of the first semiconductor chip.

What is claimed is:  
     
         1 . A semiconductor device, comprising a first semiconductor chip provided with a first electrode on a first main surface, and a second semiconductor chip provided with a second electrode on a second main surface, 
 said first and second semiconductor chips being integrated with one another so that said first and second main surfaces are opposed to one another and said first and second electrodes are electrically connected,    said second semiconductor chip having a thickness smaller than a thickness of said first semiconductor chip.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein 
 said second semiconductor chip has the thickness equal to or less than ½ of the thickness of said first semiconductor chip.    
     
     
         3 . The semiconductor device according to  claim 1 , further comprising a resin layer between said first and second main surfaces.  
     
     
         4 . The semiconductor device according to  claim 1 , further comprising a resin package to encapsulate said first and second semiconductor chips.  
     
     
         5 . The semiconductor device according to  claim 1 , wherein 
 an area of said first main surface is larger than an area of said second main surface,    a third electrode is provided outside a region of said first main surface opposed to said second main surface,    a surface opposite to said first main surface of said first semiconductor chip is adhered to a die pad,    a lead is provided adjacent to said die pad, said lead and said third electrode being connected through a bonding wire, and    said first semiconductor chip, said second semiconductor chip and the bonding wire are encapsulated in a resin package.    
     
     
         6 . The semiconductor device according to  claim 5 , wherein 
 a distance from said first main surface to a surface opposite to said second main surface of said second semiconductor chip is smaller than a distance from said first main surface to the highest position of said bonding wire on said first main surface.    
     
     
         7 . A method of manufacturing a semiconductor device comprising a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface, said method comprising: 
 a first step of integrating said first and second semiconductor chips by arranging said first and said second main surfaces to be opposed to one another and electrically connecting said first and second electrodes; and    a second step of polishing said second semiconductor chip integrated with said first semiconductor chip from an opposite side of said second main surface, so that a thickness of said second semiconductor chip is made smaller than a thickness of said first semiconductor chip.    
     
     
         8 . The method of manufacturing a semiconductor device according to  claim 7 , wherein 
 said first step comprises the step of forming a resin layer between said first and second main surfaces.    
     
     
         9 . The method of manufacturing a semiconductor device according to  claim 7 , wherein 
 said second step comprises the step of reducing the thickness of said second semiconductor chip to at most ½ of the thickness of said first semiconductor chip.    
     
     
         10 . The method of manufacturing a semiconductor device according to  claim 7 , wherein 
 an area of said first main surface is larger than an area of said second main surface,    a third electrode is provided outside a region of said first main surface opposed to said second main surface, and    said second step precedes the steps of adhering a surface opposite to said first main surface of said first semiconductor chip to a die pad; arranging a lead adjacent to said die pad and electrically connecting said lead and said third electrode through a bonding wire; and forming a resin package to encapsulate said first semiconductor chip, said second semiconductor chip and the bonding wire.    
     
     
         11 . The method of manufacturing a semiconductor device according to  claim 10 , wherein 
 said second step comprises the step of allowing a distance from said first main surface to a surface opposite to said second main surface of said second semiconductor chip to be smaller than a distance from said first main surface to the highest position of said bonding wire on said first main surface.    
     
     
         12 . A method of manufacturing a semiconductor device comprising a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface, said method comprising: 
 a first step of integrating a semiconductor wafer to be a plurality of said first semiconductor chips and a plurality of discrete said second semiconductor chips by arranging said first main surface of each said first semiconductor chip in said semiconductor wafer to be opposed to said second main surface of each said second semiconductor chip and electrically connecting said first electrode on each said first semiconductor chip in said semiconductor wafer and said second electrode on each said second semiconductor chip;    a second step of polishing said second semiconductor chip integrated with said semiconductor wafer from an opposite side of said second main surface so that a thickness of each said second semiconductor chip is made smaller than a thickness of said semiconductor wafer; and    a third step of separating said semiconductor wafer integrated with said second semiconductor chips into a plurality of discrete said first semiconductor chips, thereby forming a plurality of chip-layered bodies each including a discrete said first semiconductor chip and a discrete said second semiconductor chip integrated with one another.    
     
     
         13 . The method of manufacturing a semiconductor device according to  claim 12 , wherein 
 said first step comprises the step of forming a resin layer between said first main surface of each said first semiconductor chip in said semiconductor wafer and said second main surface of each said second semiconductor chip.    
     
     
         14 . The method of manufacturing a semiconductor device according to  claim 12 , wherein 
 said second step comprises the step of reducing the thickness of each said second semiconductor chip to at most ½ of the thickness of said semiconductor wafer.    
     
     
         15 . The method of manufacturing a semiconductor device according to  claim 12 , wherein 
 an area of said first main surface is larger than an area of said second main surface,    a third electrode is provided outside a region of said first main surface opposed to said second main surface, and    after said third step, said chip-layered bodies are each subjected to the steps of adhering a surface of said first semiconductor chip opposite to said first main surface to a die pad; providing a lead adjacent to said die pad and electrically connecting said lead and said third electrode through a bonding wire; and forming a resin package to encapsulate said first semiconductor chip, said second semiconductor chip and the bonding wire.    
     
     
         16 . The method of manufacturing a semiconductor device according to  claim 15 , wherein 
 said second step comprises the step of arranging the distance from said first main surface of each said first semiconductor chip in said semiconductor wafer to a surface of each said second semiconductor chip opposite to said second main surface to be smaller than the distance from said first main surface of each said first semiconductor chip in said semiconductor wafer to the highest position of said bonding wire on said first main surface.