Method of forming a highly integrated non-volatile semiconductor memory device

Abstract

The present invention provides a method of forming a gate structure of a floating gate MOS field effect transistor. The method comprises the steps of: forming a conductive layer on a gate insulating film; forming a dummy layer over the conductive layer; selectively forming a resist pattern over the dummy layer; carrying out an anisotropic etching process for patterning the dummy layer and the conductive layer by use of the resist pattern as a mask, thereby to form a gate structure; removing the resist pattern; forming side wall insulation films on side walls of the gate structure; forming an inter-layer insulator so that the gate structure and the side wall insulation films are completely buried within the inter-layer insulator; carrying out a first planarization process for polishing the inter-layer insulator; and carrying out a second planarization process for selectively etching the inter-layer insulator and the side wall insulation films, so that at least a top portion of the dummy layer is etched; removing the dummy layer; carrying out a third planarization process for selectively etching the inter-layer insulator and the side wall insulation films, so that a planarized surface of the inter-layer insulator and the side wall insulation films is leveled to a planarized surface of the conductive layer, wherein the dummy layer has a higher etching selectivity to the inter-layer insulator than nitride.

What is claimed is:  
     
         1 . A dummy layer pattern provided over a conductive layer pattern buried in an inter-layer insulator for protecting said conductive layer pattern from being over-polished by a chemical mechanical polishing process, 
 wherein said dummy layer pattern has a higher etching selectivity to said inter-layer insulator than nitride.    
     
     
         2 . The dummy layer pattern as claimed in  claim 1 , wherein said dummy layer pattern comprises an amorphous silicon layer.  
     
     
         3 . The dummy layer pattern as claimed in  claim 1 , wherein said dummy layer pattern comprises a polycrystalline silicon layer.  
     
     
         4 . The dummy layer pattern as claimed in  claim 1 , wherein said dummy layer pattern comprises a CVD oxide layer.  
     
     
         5 . The method as claimed in  claim 1 , wherein said dummy layer dummy layer pattern a plasma enhanced silicon oxide layer.  
     
     
         6 . The method as claimed in  claim 1 , wherein said dummy layer dummy layer pattern a boro-phospho-silicate glass layer.