Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same

Abstract

A semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having second gate electrodes includes first gate electrodes arranged a first distance apart from each other on a semiconductor substrate, second gate electrodes arranged a second distance, which is larger than the first distance, apart from each other on the semiconductor substrate, first diffusion layers formed in the semiconductor substrate, the first diffusion layers sandwiching the first gate electrodes, second diffusion layers formed in the semiconductor substrate, the second diffusion layers sandwiching the second gate electrodes, a first insulating film formed on the first diffusion layer, second insulating films formed on the side surfaces of the second gate electrodes, first silicide films formed on the first gate electrodes, second silicide films formed on the second gate electrodes, and third silicide films formed on the second diffusion layers.

What is claimed is:  
     
         1 . A semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having second gate electrodes, comprising: 
 said first gate electrodes arranged a first distance apart from each other on a semiconductor substrate;    said second gate electrodes arranged a second distance, which is larger than said first distance, apart from each other on the semiconductor substrate;    first diffusion layers formed in the semiconductor substrate, said first diffusion layers sandwiching said first gate electrodes;    second diffusion layers formed in the semiconductor substrate, said second diffusion layers sandwiching said second gate electrodes;    a first insulating film formed on said first diffusion layer;    second insulating films formed on the side surfaces of said second gate electrodes;    first silicide films formed on said first gate electrodes;    second silicide films formed on said second gate electrodes; and    third silicide films formed on said second diffusion layers.    
     
     
         2 . The semiconductor memory device according to  claim 1 , wherein the thickness A of each of said first and second insulating films as formed satisfies the relationship X/2≦A<Y/2, where X represents said first distance, and Y represents said second distance.  
     
     
         3 . The semiconductor memory device according to  claim 1 , wherein said second distance is 1.3 to 5.0 times as said first distance.  
     
     
         4 . The semiconductor memory device according to  claim 1 , wherein said first gate electrodes and said second gate electrodes are arranged apart from each other by said second distance.  
     
     
         5 . The semiconductor memory device according to  claim 1 , wherein said first insulating film fills the clearance between said first gate electrodes.  
     
     
         6 . The semiconductor memory device according to  claim 1 , wherein said first and second insulating films are formed of the same material.  
     
     
         7 . The semiconductor memory device according to  claim 1 , wherein each of said first and second insulating films is formed of an oxide film.  
     
     
         8 . The semiconductor memory device according to  claim 1 , wherein each of said first and second insulating films is formed of a silicon oxide film, a TEOS film, an ozone TEOS film, an HTO film, an SOG film, a coating type oxide film, an SA-CVD film, a plasma CVD film, or a PSG film.  
     
     
         9 . The semiconductor memory device according to  claim 1 , wherein each of said first, second and third silicide films is formed of a cobalt silicide film, a titanium silicide film or a nickel silicide film.  
     
     
         10 . The semiconductor memory device according to  claim 1 , wherein each of said first, second and third silicide films is a salicide film.  
     
     
         11 . The semiconductor memory device according to  claim 1 , wherein said first gate electrodes are the floating gate electrodes in the memory cell region of a NAND type flash memory.  
     
     
         12 . The semiconductor memory device according to  claim 1 , wherein: 
 each of said first gate electrodes includes:    a first conductive layer formed on said semiconductor substrate with a third insulating film interposed therebetween;    a fourth insulating film formed on said first conductive layer; and    a second conductive layer formed on said fourth insulating film; and    each of said second gate electrodes includes: 
 a third conductive layer formed on said semiconductor substrate with a fifth insulating film interposed therebetween; and  
 a fourth conductive layer formed on said third conductive layer.  
   
     
     
         13 . The semiconductor memory device according to  claim 12 , wherein said first conductive layer and said third conductive layers are layers of the same level, and said second conductive layer and said fourth conductive layers are layers of the same level.  
     
     
         14 . The semiconductor memory device according to  claim 12 , wherein said first conductive layer performs the function of a floating gate, and said second conductive layer performs the function of a control gate.  
     
     
         15 . The semiconductor memory device according to  claim 12 , further comprising a sixth insulating film formed between said third and fourth conductive layers and provided with an open portion allowing said third and fourth conductive layers to conduct partly with each other.  
     
     
         16 . The semiconductor memory device according to  claim 15 , wherein said open portion is positioned in the center between said third and fourth conductive layers.  
     
     
         17 . The semiconductor memory device according to  claim 15 , wherein a plurality of said open portions are formed between said third and fourth conductive layers.  
     
     
         18 . The semiconductor memory device according to  claim 1 , further comprising: 
 a third gate electrode arranged in the vicinity of said second gate electrodes and differing from said second gate electrodes in the conductivity type;    a fourth silicide film formed on said third gate electrode;    a seventh insulating film formed on the side surface of said third gate electrode;    a third diffusion layer formed in said semiconductor substrate and surrounded said third gate electrode; and    a fifth silicide film formed on said third diffusion layer.    
     
     
         19 . The semiconductor memory device according to  claim 18 , wherein said second gate electrodes and said third gate electrode are arranged apart from each other by said second distance.  
     
     
         20 . The semiconductor memory device according to  claim 1 , further comprising: 
 a fourth gate electrode arranged in the vicinity of said first gate electrodes;    a sixth silicide film formed on said fourth gate electrode;    a fourth diffusion layer formed in said semiconductor substrate and surrounded said fourth gate electrode; and    an eighth insulating film formed on said fourth diffusion layer.    
     
     
         21 . The semiconductor memory device according to  claim 20 , wherein said first gate electrodes and said fourth gate electrode are arranged apart from each other by said first distance.  
     
     
         22 . The semiconductor memory device according to  claim 20 , wherein said fourth gate electrode constitutes a gate electrode of a selecting transistor.  
     
     
         23 . A semiconductor memory device comprising: 
 a gate electrode of a first conductivity type, said gate electrode including a first conductive layer of said first conductivity type formed on a semiconductor substrate and a second conductive layer of a second conductivity type, said second conductive layer being formed on said first conductive layer.    
     
     
         24 . A semiconductor memory device comprising: 
 a first gate electrode of a first conductivity type, said first gate electrode including a first conductive layer of said first conductivity type formed on a semiconductor substrate and a second conductive layer of a second conductivity type formed on said first conductive layer; and    a second gate electrode of said second conductivity type, said second gate electrode including a third conductive layer of said second conductivity type formed on said semiconductor substrate and a fourth conductive layer of said second conductivity type formed on said third conductive layer.    
     
     
         25 . The semiconductor memory device according to  claim 24 , further comprising a third gate electrode of said second conductivity type, said third gate electrode including a fifth conductive layer of said second conductivity type formed on said semiconductor substrate, a third insulating film formed on said fifth conductive layer, and a sixth conductive layer of said second conductivity type formed on said third insulating film, said third gate electrode being formed in a memory cell region, and said first and second gate electrodes being formed in a peripheral circuit region.  
     
     
         26 . The semiconductor memory device according to  claim 24 , further comprising: 
 a first insulating film formed between said first and second conductive layers and provided with a first open portion allowing said first and second conductive layers to conduct with each other; and    a second insulating film formed between said third and fourth conductive layers and provided with a second open portion allowing said third and fourth conductive layers to conduct with each other.    
     
     
         27 . The semiconductor memory device according to  claim 26 , wherein said first open portion is positioned in the center between said first and second conductive layers, and said second open portion is positioned in the center between said third and fourth conductive layers.  
     
     
         28 . The semiconductor memory device according to  claim 26 , wherein a plurality of said first open portions are formed between said first and second conductive layers, and a plurality of said second open portions are formed between said third and fourth conductive layers.  
     
     
         29 . The semiconductor memory device according to  claim 24 , wherein each of said first to fourth conductive layers has an impurity concentration not lower than 1×10 18  cm −3 .  
     
     
         30 . The semiconductor memory device according to  claim 24 , further comprising an element separating region formed of an element separating insulating film serving to separate the element regions in said semiconductor substrate, said second conductive layer and said fourth conductive layer being formed contiguous to each other on said element separating insulating film.  
     
     
         31 . The semiconductor memory device according to  claim 24 , wherein each of said first and third conductive layers is of a two-layer structure.  
     
     
         32 . The semiconductor memory device according to  claim 25 , wherein each of said first, third and fifth conductive layers is of a two-layer structure.  
     
     
         33 . The semiconductor memory device according to  claim 24 , wherein said first conductivity type is P-type, and said second conductivity type is N-type.  
     
     
         34 . The semiconductor memory device according to  claim 25 , wherein said fifth conductive layer performs the function of a floating gate, and said sixth conductive layer performs the function of a control gate.  
     
     
         35 . A method of manufacturing a semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having said gate electrodes, comprising: 
 forming on a semiconductor substrate said first gate electrodes arranged apart from each other by a first distance and said second gate electrodes arranged apart from each other by a second distance larger than said first distance;    forming a first diffusion layer in said semiconductor substrate to surround said first gate electrodes;    forming a first insulating film on said first diffusion layer and the side surfaces of said second gate electrodes;    forming a second diffusion layer in said semiconductor substrate to surround said second gate electrodes; and    forming first, second and third silicide films on said first gate electrodes, on said second gate electrodes and on said second diffusion layer, respectively.    
     
     
         36 . A method of manufacturing a semiconductor memory device comprising a memory cell region having first gate electrodes formed of first and second conductive layers and a peripheral circuit region having second gate electrodes formed of third and fourth conductive layers, comprising: 
 forming a first insulating film on a semiconductor substrate;    forming a first electrode material layer into which an impurity is not introduced on said first insulating film;    forming an element separating region in said first electrode material layer, said first insulating film, and said semiconductor substrate, said element separating region formed of an element separating insulating film;    forming said first conductive layer by applying ion implantation and annealing to said first electrode material layer in said memory cell region;    forming a second insulating film on said first conductive layer;    forming a second electrode material layer on said second insulating film and said first conductive material layer, said second electrode material layer being not introduced an impurity;    selectively removing said first and second electrode material layers, said first conductive layer and said second insulating film to form a pattern of said first gate electrodes arranged apart from each other by a first distance and a pattern of said second gate electrodes arranged apart from each other by a second distance larger than said first distance;    forming a fist diffusion layer in said semiconductor substrate to surround said first gate electrodes;    forming a third insulating film on said first diffusion layer and the side surfaces of said second gate electrodes;    applying ion implantation and annealing to form said second conductive layer on said first conductive layer, to form third and fourth conductive layers, and to form a second diffusion layer in said semiconductor substrate; and    forming first, second and third silicide films on said second conductive layer, on said fourth conductive layer, and on said second diffusion layer, respectively.    
     
     
         37 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein the thickness A of said third insulating film as formed satisfies the relationship X/2≦A<Y/2, where X represents said first distance, and Y represents said second distance.  
     
     
         38 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein said second distance is 1.3 to 5.0 times as said first distance.  
     
     
         39 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein said third insulating film fills the clearance between said first gate electrodes.  
     
     
         40 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein said third insulating film is an oxide film.  
     
     
         41 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein said third insulating film is formed of a silicon oxide film, a TEOS film, an ozone TEOS film, HTO film, an SOG film, a coating type oxide film, an SA-CVD film, a plasma CVD film or a PSG film.  
     
     
         42 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein each of said first, second and third silicide films is formed of a cobalt silicide film, a titanium silicide film or a nickel silicide film.  
     
     
         43 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein each of said first, second and third silicide films is a salicide film.  
     
     
         44 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein said first gate electrodes are the floating gate electrodes in a memory cell region of a NAND type flash memory.  
     
     
         45 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein said first conductive layer performs the function of a floating gate, and said second conductive layer performs the function of a control gate.  
     
     
         46 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein the surface of said element separating insulating film is positioned lower than the surface of said first electrode material layer by partly removing said element separating insulating film after formation of said element separating region.  
     
     
         47 . The method of manufacturing a semiconductor memory device according to  claim 36 , further comprising: 
 forming a fourth insulating film between said third and fourth conductive layers; and    forming an open portion in said fourth insulating film.    
     
     
         48 . The method of manufacturing a semiconductor memory device according to  claim 47 , wherein said open portion is positioned in the center between said third and fourth conductive layers.  
     
     
         49 . The method of manufacturing a semiconductor memory device according to  claim 47 , wherein a plurality of said open portions are formed between said third and fourth conductive layers.  
     
     
         50 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein, where said first gate electrodes and said second gate electrodes are of the same conductivity type, said third conductive layer is formed simultaneously in forming said first conductive layer.  
     
     
         51 . The method of manufacturing a semiconductor memory device according to  claim 36 , wherein each of said first conductive layer in said first gate electrodes and said third conductive layer in said second gate electrodes is formed by using an electrode material into which an impurity is not introduced.  
     
     
         52 . The method of manufacturing a semiconductor memory device according to  claim 36 , further comprising: 
 forming a third gate electrode in the vicinity of said first gate electrodes;    forming a third diffusion layer in said semiconductor substrate to surround said third gate electrode;    forming a fifth insulating film on said third diffusion layer; and    forming a fourth silicide film on said third gate electrode.    
     
     
         53 . The method of manufacturing a semiconductor memory device according to  claim 52 , wherein said first gate electrodes and said third gate electrode are arranged apart from each other by said first distance.  
     
     
         54 . The method of manufacturing a semiconductor memory device according to  claim 52 , wherein said third electrode are a gate electrode of a selecting transistor.  
     
     
         55 . A method of manufacturing a semiconductor memory device including a first region having a first gate electrode of a first conductivity type formed of first and second conductive layers and a second region having a second gate electrode of a second conductivity type formed of third and fourth conductive layers, comprising: 
 forming a first insulating film on a semiconductor substrate;    forming a first electrode material layer on said first insulating film;    forming an element separating region in said first electrode material layer, said first insulating film and said semiconductor substrate, said element separating region formed of an element separating insulating film;    applying ion implantation and annealing to said first electrode material layer in said second region to form said third conductive layer of said second conductivity type;    applying ion implantation and annealing to said first electrode material layer in said first region to form said first conductive layer of said first conductivity type; and    forming a second electrode material layer of said second conductivity type in said first conductive layer, said third conductive layer and said element separating insulating film and forming said second conductive layer and said fourth conductive layer each formed of said second conductive material layer.    
     
     
         56 . The method of manufacturing a semiconductor memory device according to  claim 55 , wherein said first electrode material layer is formed of a first layer and a second layer, any one of said first layer and second layer being a layer having an impurity of said first conductivity type implanted thereinto and said impurity being diffused by annealing into the other layer to form said third conductive layer.  
     
     
         57 . The method of manufacturing a semiconductor memory device according to  claim 55 , further comprising: 
 forming said second insulating film to be positioned between said first and second conductive layers and between said third and fourth conductive layers; and    forming open portions in said second insulating film to permit said first conductive layer to conduct with said second conductive layer and to permit said third conductive layer to conduct with said fourth conductive layer.    
     
     
         58 . The method of manufacturing a semiconductor memory device according to  claim 57 , wherein said open portions are formed in the center between said first and second conductive layers and in the center between said third and fourth conductive layers.  
     
     
         59 . The method of manufacturing a semiconductor memory device according to  claim 57 , wherein a plurality of said open portions are formed between said first and second conductive layers and between said third and fourth conductive layers.  
     
     
         60 . The method of manufacturing a semiconductor memory device according to  claim 55 , wherein each of said first to fourth conductive layers has an impurity concentration not lower than 1×10 18  cm −3 .  
     
     
         61 . The method of manufacturing a semiconductor memory device according to  claim 55 , wherein said second conductive layer and said fourth conductive layer are formed contiguous on said element separating insulating film.  
     
     
         62 . The method of manufacturing a semiconductor memory device according to  claim 55 , wherein said first conductivity type is P-type and said second conductivity type is N-type.  
     
     
         63 . A method of manufacturing a semiconductor memory device provided with a peripheral circuit region having a first region including a first gate electrode of a first conductivity type formed of first and second conductive layers and a second region including a second gate electrode of a second conductivity type formed of third and fourth conductive layers, and with a memory cell region having a third gate electrode of said second conductivity type formed of fifth and sixth conductive layers, comprising: 
 forming a first insulating film on a semiconductor substrate;    forming a first electrode material layer on said first insulating film;    forming an element separating region in said first electrode layer, said first insulating film and said semiconductor substrate, said element separating region formed of an element separating insulating film;    applying ion implantation and annealing to said first electrode material layer positioned in said second region and said memory cell region to form said third conductive layer and said fifth conductive layer of said second conductivity type;    applying ion implantation and annealing to said first electrode material layer in said first region to form said first conductive layer of said first conductivity type;    forming a second insulating film on said fifth conductive layer; and    forming a second electrode material layer of said second conductivity type in said second insulating film, said first conductive layer, said third conductive layer and said element separating insulating film, followed by patterning said second electrode material layer to form said second conductive layer, said fourth conductive layer and said sixth conductive layer each formed of said second electrode material layer.    
     
     
         64 . The method of manufacturing a semiconductor memory device according to  claim 63 , wherein said first electrode material layer is formed of a first layer and a second layer, any one of said first layer and second layer being a layer having an impurity of said first conductivity type implanted thereinto and said impurity being diffused by annealing into the other layer to form said third conductive layer and said fifth conductive layer.  
     
     
         65 . The method of manufacturing a semiconductor memory device according to  claim 63 , further comprising: 
 forming said second insulating film to be positioned between said first and second conductive layers and between said third and fourth conductive layers; and    forming open portions in said second insulating film to permit said first conductive layer to conduct with said second conductive layer and to permit said third conductive layer to conduct with said fourth conductive layer.    
     
     
         66 . The method of manufacturing a semiconductor memory device according to  claim 65 , wherein said open portions are formed in the center between said first and second conductive layers and in the center between said third and fourth conductive layers.  
     
     
         67 . The method of manufacturing a semiconductor memory device according to  claim 65 , wherein a plurality of said open portions are formed between said first and second conductive layers and between said third and fourth conductive layers.  
     
     
         68 . The method of manufacturing a semiconductor memory device according to  claim 63 , wherein each of said first to sixth conductive layers has an impurity concentration not lower than 1×10 18  cm −3 .  
     
     
         69 . The method of manufacturing a semiconductor memory device according to  claim 63 , wherein said second conductive layer and said fourth conductive layer are formed contiguous on said element separating insulating film.  
     
     
         70 . The method of manufacturing a semiconductor memory device according to  claim 63 , wherein said first conductivity type is P-type and said second conductivity type is N-type.  
     
     
         71 . The method of manufacturing a semiconductor memory device according to  claim 63 , wherein said fifth conductive layer performs the function of a floating gate and said sixth conductive layer performs the function of a control gate.