Semiconductor device and method for fabricating the same

Abstract

Semiconductor device and method for fabricating the same, the device including a semiconductor substrate, a recessed channel region recessed below a surface of the semiconductor substrate, and a gate oxide film formed on the recessed channel region, a first and a second lightly doped impurity regions in surfaces of the substrate adjacent to, and on both sides of the recessed channel region respectively, and a first and a second highly doped impurity regions adjacent to the first and second lightly doped impurity regions, respectively, inverted sidewalls on the first and second lightly doped impurity regions each having a round in a side of the recessed channel region, and a gate electrode both on the inverted sidewalls and the recessed channel region, whereby securing a fabrication allowance and improving a device packing density.

What is claimed is:  
     
         1 . A semiconductor device having a unit cell comprising: 
 a semiconductor substrate;    a recessed channel region recessed below a surface of the semiconductor substrate, and a gate oxide film formed on the recessed channel region;    a first and a second lightly doped impurity regions in surfaces of the substrate adjacent to, and on both sides of the recessed channel region respectively, and a first and a second highly doped impurity regions adjacent to the first and second lightly doped impurity regions, respectively;    inverted sidewalls on the first and second lightly doped impurity regions each having a round in a side of the recessed channel region; and,    a gate electrode both on the inverted sidewalls and the recessed channel region.    
     
     
         2 . A semiconductor device as claimed in  claim 1 , wherein the recessed channel region a semispherical form having a deepest central portion, and shallowest both sides adjacent to the first and second lightly doped impurity regions.  
     
     
         3 . A semiconductor device as claimed in  claim 1 , wherein the inverted sidewalls have vertical forms in outer sides of the recessed channel region.  
     
     
         4 . A semiconductor device as claimed in  claim 1 , wherein the gate electrode has a uniform thickness and a lowest central portion identical to a form of the recessed channel region.  
     
     
         5 . A semiconductor device comprising: 
 device isolating layers in device isolating regions of a semiconductor substrate;    a recessed channel region recessed to a depth in a semispherical form in an active region defined by the device isolating layers;    a gate oxide film formed on the recessed channel region;    lightly doped impurity regions adjacent to, and on both sides of the recessed channel region respectively, and inverted sidewalls on the lightly doped impurity regions each having a round in a side ofthe recessed channel region and a vertical form in an outer side of the recessed channel region;    a gate electrode both on the inverted sidewalls and the recessed channel region;    highly doped impurity regions on both sides of the gate electrode aligned with the inverted sidewalls and adjacent to the LDD regions;    an interlayer insulating layer on an entire surface having contact holes of certain sizes to the highly doped impurity regions; and,    metal electrode layers in contact with the highly doped impurity regions through the contact holes in the interlayer insulating layer.    
     
     
         6 . A semiconductor device as claimed in  claim 5 , wherein the device isolating layer has an STI structure formed by etching the device isolating region of the semiconductor substrate to a depth to form trenches, and planarizing after stuffing the trenches with an insulating material.  
     
     
         7 . A semiconductor device as claimed in  claim 5 , wherein the gate electrode includes a bottom portion positioned below a surface of the substrate and a top portion recessed identical to, and as much as a recessed depth of the recessed channel region according to a form of the recessed channel region.  
     
     
         8 . A semiconductor device as claimed in  claim 5 , wherein a distance alone a surface of the channel region is greater than a horizontal distance between the LDD regions.  
     
     
         9 . A method for fabricating a semiconductor device, comprising the steps of: 
 (1) forming an oxide film and a nitride film on a semiconductor substrate in succession and patterning selectively, and forming trenches using the patterned oxide film and the nitride film;    (2) stuffing an insulating material in the trenches, to form device isolating layers;    (3) removing a width of the nitride film on an active region defined by the device isolating layers, to form a channel defining trench;    (4) using the patterned nitride film as a mask in implanting impurities lightly, to form lightly doped impurity regions for forming LDDs;    (5) forming inverted sidewalls at sides of the channel defining trench, and oxidizing a bottom portion, to form the LDD regions;    (6) removing the oxide film on a bottom surface of the channel defining trench, to form a channel of semispherical recess with a depth;    (7) removing the nitride layer, forming a gate oxide film on a surface of a recessed channel region, and forming a gate electrode both on the inverted sidewalls and the gate oxide film; and,    (8) using the gate electrode inclusive of the inverted sidewalls as a mask in implanting impurities, heavily.    
     
     
         10 . A method as claimed in  claim 9 , wherein the nitride film has a thickness of 1400˜1600Å.  
     
     
         11 . A method as claimed in  claim 9 , wherein the formation of the inverted sidewalls in the step (5) includes the steps of; 
 forming, and etching back an HLD layer on an entire surface having the lightly doped impurity regions for forming the LDDs formed therein.    
     
     
         12 . A method as claimed in  claim 11 , wherein the inverted sidewalls have a height fixed by a thickness of the nitride film.  
     
     
         13 . A method as claimed in  claim 9 , wherein the step (6) is carried out by wet etching.  
     
     
         14 . A method as claimed in  claim 9 , wherein the formation of a gate electrode in the step (7) includes the steps of: 
 forming a polysilicon layer on an entire surface having the inverted sidewalls and the gate oxide film formed thereon, and    selectively patterning the polysilicon layer by photolithography,    thereby forming the gate electrode having a bottom portion positioned below a surface of the substrate and a top portion recessed identical to, and as much as a recessed depth of the recessed channel region according to a form of the recessed channel region.