US2003025123A1PendingUtilityA1

Semiconductor laser device and method for fabricating the same

Assignee: MATSUSHITA ELECTRIC INDUSTRIAL CO LTDPriority: Jul 26, 2001Filed: Jul 26, 2002Published: Feb 6, 2003
Est. expiryJul 26, 2021(expired)· nominal 20-yr term from priority
H01S 5/2231H01S 5/164H01S 5/34326H01S 5/3072B82Y 20/00H01S 5/3436
42
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A semiconductor laser device according to the present invention has a semiconductor substrate, an active layer formed on the semiconductor substrate and made of a compound semiconductor containing phosphorus, a guide layer formed on the active layer and made of a compound semiconductor, a dopant diffusion preventing layer formed on the guide layer and made of a semiconductor compound containing arsenic, and a clad layer formed on the dopant diffusion preventing layer and made of a compound semiconductor containing a dopant.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A semiconductor laser device comprising: 
 a semiconductor substrate;    an active layer formed on the semiconductor substrate and made of a compound semiconductor containing phosphorus;    a guide layer formed on the active layer and made of a compound semiconductor;    a dopant diffusion preventing layer formed on the guide layer and made of a compound semiconductor containing arsenic; and    a clad layer formed on the dopant diffusion preventing layer and made of a compound semiconductor containing a dopant.    
     
     
         2 . The device of  claim 1 , wherein a concentration of the dopant in the clad layer is in a range of 5×10 17  atoms cm −3  to 1×10 19  atoms cm −3 .  
     
     
         3 . The device of  claim 1 , wherein the dopant is zinc.  
     
     
         4 . The device of  claim 1 , wherein a thickness of the guide layer is in a range of 10 nm to 50 nm.  
     
     
         5 . The device of  claim 1 , wherein a thickness of the dopant diffusion preventing layer is 2 nm or more.  
     
     
         6 . The device of  claim 5 , wherein a thickness of the dopant diffusion preventing layer is 50 nm or less.  
     
     
         7 . The device of  claim 1 , wherein 
 the semiconductor substrate is made of GaAs,    the active layer is made of (Al x Ga 1−x ) 1−y In y P (0≦x≦1, 0≦y≦1), and    the dopant diffusion preventing layer is made of Al z Ga 1−z As (0≦z≦1).    
     
     
         8 . The device of  claim 7 , wherein the dopant diffusion preventing layer includes a layer made of Al w Ga 1−w As (0<w≦1) and a layer made of GaAs which are alternately deposited.  
     
     
         9 . The device of  claim 1 , wherein the compound semiconductor making the dopant diffusion preventing layer further contains carbon, beryllium, or magnesium.  
     
     
         10 . The device of  claim 1 , wherein the compound semiconductor making the dopant diffusion preventing layer further contains silicon or selenium.  
     
     
         11 . The device of  claim 1 , wherein the active layer has a first region including two types of layers made of compound semiconductors with different band gaps and alternately deposited and a second region made of alloyed compound semiconductors with different band gaps and adjacent to the first region.  
     
     
         12 . A method for fabricating a semiconductor laser device, the method comprising the steps of: 
 (a) successively depositing, on a semiconductor substrate, an active layer made of a compound semiconductor containing phosphorus and a guide layer made of a compound semiconductor;    (b) depositing, on the substrate, a dopant diffusion preventing layer made of a compound semiconductor containing arsenic; and    (c) depositing, on the substrate, a first clad layer made of a compound semiconductor containing a dopant.    
     
     
         13 . The method of  claim 12 , further comprising the steps of: 
 (d) after the step (c), depositing, on the substrate, a current block layer made of a compound semiconductor;    (e) forming an opening configured as a stripe in the current block layer; and    (f) depositing, on the substrate, a second clad layer made of a compound semiconductor containing a dopant.    
     
     
         14 . The method of  claim 12 , further comprising the steps of: 
 (d) after the step (c), successively depositing, on the substrate, an etching stop layer, a second clad layer made of a compound semiconductor containing a dopant, and a cap layer;    (g) forming, on the cap layer, a mask having an opening;    (h) removing, by using the mask, respective regions of the second clad layer and the cap layer located within the opening to expose the etching stop layer in the opening; and    (i) forming, on the substrate, a current block layer made of a compound semiconductor.    
     
     
         15 . The method of  claim 12 , further comprising the steps of 
 (k) after the step (c), forming, on the substrate, a first mask having a first opening;    (l) forming, by using the first mask, a first region from which the respective regions of the dopant diffusion preventing layer and the first clad layer located within the first opening have been removed and a second region in which the dopant diffusion preventing layer and the first clad layer are deposited;    (m) depositing, on the substrate, the first clad layer again and further successively depositing an etching stop layer, a second clad layer made of a compound semiconductor containing a dopant, and a cap layer;    (n) forming a mask for dopant diffusion on the second region of the substrate and performing a thermal treatment;    (o) removing the mask for dopant diffusion and then forming a second mask having an opening extending crosswise over the first and second regions of the substrate;    (p) removing, by using the second mask, the regions of the second clad layer and the cap layer located within the second opening to expose the etching stop layer in the second opening; and    (q) forming, on the substrate, a current block layer made of a compound semiconductor.

Join the waitlist — get patent alerts

Track US2003025123A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.