US2003023776A1PendingUtilityA1

Method for enabling a communication between processes, processing system, integrated chip and module for such a chip

Assignee: NOKIA CORPPriority: Jun 28, 2001Filed: Jun 27, 2002Published: Jan 30, 2003
Est. expiryJun 28, 2021(expired)· nominal 20-yr term from priority
G06F 13/387Y02D10/00G06F 9/45533G06F 9/546
41
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

The invention relates to a method for enabling in a processing system a communication between at least two activated processes 22,23. In order to improve the communication between different processes 22,23 of a processing system, it is proposed that for said communication signals are transmitted between said at least two processes 22,23 in virtual channels using the same physical channel 28. This enables an efficient use of physical resources. A corresponding processing system comprises at least one processor 50 - 52 for running different processes, at least one physical channel provided for enabling a communication between at least two of said different processes, and means 55 - 57 for distributing signals which are to be transmitted for such a communication between said at least two different processes to different virtual channels on said at least one physical channel.

Claims

exact text as granted — not AI-modified
1 . Method for enabling in a processing system a communication between at least two activated processes ( 22 , 23 ), wherein for said communication signals are transmitted between said at least two processes ( 22 , 23 ) in at least two virtual channels using the same physical channel ( 28 ).  
     
     
         2 . Method according to  claim 1 , wherein different kinds of signals are transmitted between said processes ( 22 , 23 ) in different virtual channels using the same physical channel ( 28 ).  
     
     
         3 . Method according to  claim 2 , wherein said different kinds of signals include notification signals and data signals.  
     
     
         4 . Method according to  claim 2 , wherein different priorities are assigned to said different kinds of signals for transmission in different virtual channels using the same physical channel ( 28 ).  
     
     
         5 . Method according to  claim 1 , wherein said processes ( 22 , 23 ) between which a communication is to be enabled are hardware and/or software implemented processes.  
     
     
         6 . Method according to  claim 1 , wherein said processes ( 22 , 23 ) are implemented on at least two different chips ( 20 , 21 ).  
     
     
         7 . Method according to  claim 6 , wherein a dedicated process in each chip handles the communication.  
     
     
         8 . Method according to  claim 7 , wherein said process for handling the communication in each chip is implemented in software or hardware.  
     
     
         9 . Processing system comprising at least one processor ( 50 - 52 ) for running different processes, at least one physical channel provided for enabling a communication between at least two of said different processes, and means ( 55 - 57 ) for distributing signals which are to be transmitted for such a communication between said at least two different processes to different virtual channels on said at least one physical channel.  
     
     
         10 . Processing system according to  claim 9 , wherein said means ( 55 - 57 ) for distributing signals to different virtual channels include means for assigning different priorities to different kinds of signals that are to be transmitted between said different processes.  
     
     
         11 . Processing system according to  claim 9  comprising several chips, wherein each of at least two of said chips includes at least one processor ( 50 - 52 ) for running at least one process, wherein each of said at least two chips has access to the at least one physical channel, and wherein said means ( 55 - 57 ) for distributing signals to different virtual channels include a dedicated process in each chip for controlling the communication between the different processes of the processing system.  
     
     
         12 . Processing system according to  claim 9 , wherein a software process is employed for controlling the communication between said at least two different processes, which software process is implemented in a microprocessor unit for handling the access of said different processes to said at least one physical channel.  
     
     
         13 . Processing system according to  claim 9 , wherein a hardware process is employed for controlling the communication between the different processes, which hardware process is implemented in a communication assistance hardware ( 55 ) for handling the access of said different processes to said at least one physical channel.  
     
     
         14 . Processing system according to  claim 9 , wherein said at least one physical channel is a bi-directional bus.  
     
     
         15 . Processing system according to  claim 9 , wherein said processes between which a communication is to be enabled are hardware and/or software implemented processes.  
     
     
         16 . Processing system according to  claim 9 , wherein said means ( 55 - 57 ) for distributing signals are designed to be independent from specific processes of said processing system.  
     
     
         17 . Processing system according to  claim 9 , wherein said processing system is a real-time communications system.  
     
     
         18 . Integrated chip comprising at least one processor ( 50 - 52 ) for running at least two different processes in said integrated chip, at least one physical channel provided for enabling a communication between different processes run in said integrated chip, and means ( 55 - 57 ) according to  claim 9  for distributing signals that are to be transmitted for such a communication between processes run in said integrated chip to different virtual channels on said at least one physical channel.  
     
     
         19 . Integrated chip comprising at least one processor ( 50 - 52 ) for running at least one process in said integrated chip, an interface ( 64 , 74 ) to at least one external physical channel provided for enabling a communication between said at least one process in said integrated chip and at least one other process running in another integrated chip, and means ( 55 - 57 ) according to  claim 9  for distributing signals that are to be transmitted for such a communication between processes running in said integrated chip and in another integrated chip to different virtual channels using said at least one external physical channel.  
     
     
         20 . Module for an integrated chip comprising means ( 55 - 57 ) according to  claim 9  for distributing signals that are to be transmitted between different processes running in said integrated chip and/or between a process running in said integrated chip and a process running in another integrated chip for enabling a communication between said processes to virtual channels on a physical channel within said integrated chip and/or a physical channel connecting said integrated chip and another integrated chip.

Join the waitlist — get patent alerts

Track US2003023776A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.