US2003022110A1PendingUtilityA1

Degradation-free low-permittivity dielectrics patterning process for damascene

41
Priority: May 22, 1998Filed: Sep 20, 2002Published: Jan 30, 2003
Est. expiryMay 22, 2018(expired)· nominal 20-yr term from priority
Inventors:Yimin Huang
H10P 50/287H10P 50/283H10P 50/73H10W 20/074H10W 20/081
41
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Claims

Abstract

A degradation-free, low-permissivity dielectrics patterning process for damascene starts with provision of a substrate, wherein the substrate has a dielectric layer and a via plug formed on it. Then, a inter-metal dielectric layer and an insulating layer are formed in sequence on the dielectric layer. A hard mask layer is next formed on the insulating layer, and is subsequently patterned. An etching process is performed on the insulating layer and the inter metal dielectric layer by using the patterned hard mask layer as a mask to form a metal line trench and expose the via plug. The metal line trench is then filled with metal by forming a metal layer on the hard mask layer. A metal line in the shallow trench is formed by performing chemical mechanical polishing on the metal layer to expose the insulating layer, and then performing post-chemical mechanical polishing cleaning.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A degradation-free, low-permissivity dielectric patterning process for damascene, the process comprising: 
 providing a substrate, wherein the substrate has a dielectric layer and a via plug formed on it;    forming a inter-metal dielectric layer on the dielectric layer, wherein the inter metal dielectric layer has a thickness;    forming an insulating layer on the inter metal dielectric layer, wherein the insulating layer has a thickness;    forming a hard mask layer on the insulating layer, wherein the hard mask layer has a thickness;    forming and patterning a photoresist layer on the hard mask layer to expose a portion of the hard mask layer;    performing an etching process on the hard mask layer until the insulating layer is exposed to from a shallow trench;    performing oxygen plasma ashing and wet chemical cleaning to remove the photoresist layer;    performing an etching process on the insulating layer and the inter-metal dielectric layer by using the hard mask layer as a mask to form a metal line trench and expose the via plug;    forming a glue/barrier layer conformal to the metal line trench and the hard mask layer;    forming a metal layer on the glue/barrier layer to fill the metal line trench;    performing chemical mechanical polishing on the metal layer to expose the insulating layer and form a metal line in the shallow trench, wherein the metal line is electrically connected to the via plug; and    performing post-chemical mechanical polishing cleaning.    
     
     
         2 . The process of  claim 1 , wherein inter-metal dielectric layer includes HSQ, FSG, flare, SILK or parylene.  
     
     
         3 . The process of  claim 1 , wherein the thickness of the inter metal dielectric layer is about 5000-7000 Å.  
     
     
         4 . The process of  claim 1 , wherein the insulating layer includes silicon oxide.  
     
     
         5 . The process of  claim 1 , wherein the thickness of the insulating layer is about 2000 Å.  
     
     
         6 . The process of  claim 1 , wherein the hard mask layer includes titanium, titanium nitride, tantalum, tantalum nitride, or tungsten nitride.  
     
     
         7 . The process of  claim 1 , wherein the thickness of the hard mask layer is about 300-500 Å.  
     
     
         8 . The process of  claim 1 , wherein the steps of forming the hard mask layer includes reactive ion etching.  
     
     
         9 . The process of  claim 1 , wherein the etching process performed on the insulating layer and the inter metal dielectric layer includes reactive ion etching.  
     
     
         10 . The process of  claim 1 , wherein the glue/barrier layer includes titanium, titanium nitride, tantalum, tantalum nitride, or tungsten nitride.  
     
     
         11 . A degradation-free, low-permissivity dielectrics patterning process for damascene on a substrate, wherein the substrate has a dielectric layer and a via plug formed thereon, the process comprising: 
 forming an inter-metal dielectric layer on the dielectric layer, wherein the inter-metal dielectric layer has a thickness;    forming an insulating layer on the inter-metal dielectric layer, wherein the insulating layer has a thickness;    forming a hard mask layer on the insulating layer, wherein the hard mask layer has a thickness;    patterning the hard mask layer to form a shallow trench and expose the insulating layer;    performing an etching process on the insulating layer and the inter-metal dielectric layer by using the hard mask layer as a mask to form a metal line trench and expose the via plug;    forming a metal layer on the hard mask layer to fill the metal line trench; and    performing chemically mechanical polishing on the metal layer to expose the insulating layer and form a metal line in the shallow trench, wherein the metal line is electrically connected to the via plug.    
     
     
         12 . The process of  claim 11 , wherein inter metal dielectric layer includes HSQ, FSG, flare, SILK or parylene.  
     
     
         13 . The process of  claim 11 , wherein the thickness of the inter metal dielectric layer is about 5000-7000 Å.  
     
     
         14 . The process of  claim 11 , wherein the insulating layer includes silicon oxide.  
     
     
         15 . The process of  claim 11 , wherein the thickness of the insulating layer is about 2000 Å.  
     
     
         16 . The process of  claim 11 , wherein the hard mask layer includes titanium, titanium nitride, tantalum, tantalum nitride, or tungsten nitride.  
     
     
         17 . The process of  claim 11 , wherein the thickness of the hard mask layer is about 300-500 Å.  
     
     
         18 . The process of  claim 11 , wherein the steps of patterning the hard mask layer comprise: 
 forming a photoresist layer on the hard mask layer, wherein the photoresist layer exposes a portion of the hard mask layer;    performing an etching process to form the shallow trench and expose the insulating layer; and    removing the photoresist layer by oxygen plasma ashing and wet chemical cleaning.    
     
     
         19 . The process of  claim 18 , wherein the etching process performed on the hard mask layer includes reactive ion etching.  
     
     
         20 . The process of  claim 11 , wherein the etching process performed on the insulating layer and the inter metal dielectric layer includes reactive ion etching.  
     
     
         21 . The process of  claim 11 , wherein the steps of forming the metal layer further comprises forming a glue/barrier layer conformal to the hard mask layer and the metal line trench.  
     
     
         22 . The process of  claim 21 , wherein the glue/barrier layer includes titanium, titanium nitride, tantalum, tantalum nitride, or tungsten nitride.  
     
     
         23 . The process of  claim 11 , wherein the steps of removing the metal layer on the bard mask layer comprises performing chemical mechanical polishing and post-chemical mechanical polishing cleaning.  
     
     
         24 . A degradation-free, low-permissivity dielectrics patterning process for damascene on a substrate, wherein the substrate has a dielectric layer and a via plug formed thereon, the process comprising: 
 forming a inter metal dielectric layer on the dielectric layer, wherein the inter metal dielectric layer has a thickness;    forming a hard mask layer on the insulating layer, wherein the hard mask layer has a thickness;    patterning the hard mask layer to form a shallow trench and expose a portion of the inter layer;    performing an etching process on the inter metal dielectric layer by using the hard mask layer as a mask to form a metal line trench and expose the via plug;    forming a metal layer on the hard mask layer to fill the metal line trench; and    performing an etching process on the metal layer to expose the insulating layer and form a metal line in the shallow trench, wherein the metal line is electrically connected to the via plug.    
     
     
         25 . The process of  claim 24 , wherein inter-metal dielectric layer includes HSQ, FSG, flare, SILK or parylene.  
     
     
         26 . The process of  claim 24 , wherein the thickness of the inter metal dielectric layer is about 5000-7000 Å.  
     
     
         27 . The process of  claim 24 , wherein the process furthers comprises forming an insulating layer before forming the hard mask layer, wherein the insulating layer has a thickness.  
     
     
         28 . The process of  claim 27 , wherein the insulating layer includes silicon oxide.  
     
     
         29 . The process of  claim 27 , wherein the thickness of the insulating layer is about 2000 Å.  
     
     
         30 . The process of  claim 24 , wherein the hard mask layer includes titanium, titanium nitride, tantalum, tantalum nitride, or tungsten nitride.  
     
     
         31 . The process of  claim 24 , wherein the thickness of the hard mask layer is about 300-500 Å.  
     
     
         32 . The process of  claim 24 , wherein the steps of patterning the hard mask layer comprise: 
 forming a photoresist layer on the hard mask layer, wherein the photoresist layer exposes a portion of the hard mask layer;    performing an etching process to form the shallow trench and expose the insulating layer; and    removing the photoresist layer by oxygen plasma ashing and wet chemical cleaning.    
     
     
         33 . The process of  claim 32 , wherein the etching process performed on the hard mask layer includes reactive ion etching.  
     
     
         34 . The process of  claim 24 , wherein the etching process performed on the inter metal dielectric layer includes reactive ion etching.  
     
     
         35 . The process of  claim 24 , wherein the steps of forming the metal layer further comprise forming a glue/barrier layer conformal to the hard mask layer and the metal line trench, wherein the glue/barrier layer further has contact with the dielectric layer.  
     
     
         36 . The process of  claim 35 , wherein the glue/barrier layer includes titanium, titanium nitride, tantalum, tantalum nitride, or tungsten nitride.  
     
     
         37 . The process of  claim 24 , wherein the steps of removing the metal layer on the hard mask layer comprises performing chemically mechanical polishing and post-chemical mechanical polishing cleaning.

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