Semiconductor device and process for production thereof

Abstract

The present invention provides a semiconductor device comprising: a semiconductor substrate having semiconductor elements, and a plurality of wirings formed on the semiconductor substrate via an isolation film, wherein the wirings are formed in at least one layer level so that the region in which the wirings are formed is divided into a wiring region of small wiring-to-wiring distance and a wiring region of large wiring-to-wiring distance; a first inter-level isolation film is selectively formed in the wiring region of small wiring-to-wiring distance and a second inter-level isolation film is formed in the wiring region of large wiring-to-wiring distance to cover the wirings; throughholes are formed only in the second inter-level isolation film; and the dielectric constant of the first inter-level isolation film is smaller than the dielectric constant of the second inter-level isolation film. This semiconductor device has a fine multi-layered wiring structure of high performance and remarkably improved reliability.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a semiconductor substrate having semiconductor elements, and    a plurality of wirings formed on the semiconductor substrate via an isolation film, wherein the wirings are formed in at least one layer level so that the region in which the wirings are formed is divided into a wiring region of small wiring-to-wiring distance and a wiring region of large wiring-to-wiring distance; a first inter-level isolation film is selectively formed in the wiring region of small wiring-to-wiring distance and a second inter-level isolation film is formed in the wiring region of large wiring-to-wiring distance to cover the wirings; throughholes are formed only in the second inter-level isolation film; and the dielectric constant of the first inter-level isolation film is smaller than the dielectric constant of the second inter-level isolation film.    
     
     
         2 . A semiconductor device according to  claim 1 , comprising: 
 a semiconductor substrate having semiconductor elements, and    a plurality of wirings formed on the semiconductor substrate via an isolation film, wherein the wirings are formed in at least one layer level so that the region in which the wirings are formed is divided into a wiring region of small wiring-to-wiring distance and a wiring region of large wiring-to-wiring distance; a first inter-level isolation film is selectively formed in the wiring region of small wiring-to-wiring distance, a second inter-level isolation film is formed in the wiring region of large wiring-to-wiring distance to cover the wirings; and a third inter-level isolation film is formed so as to cover the first inter-level-isolation film and the second inter-level isolation film; throughholes are formed only in the second inter-level isolation film and the third inter-level isolation film; and the dielectric constant of the first inter-level isolation film is smaller than the dielectric constants of the second inter-level isolation film and the third inter-level isolation film.    
     
     
         3 . A semiconductor device according to  claim 1 , wherein the isolation film on the substrate is dented at the surface areas corresponding to the wiring region of small wiring-to-wiring distance but not covered by the wirings of the region and the resulting dents are filled with the first inter-level isolation film.  
     
     
         4 . A semiconductor device according to  claim 2 , wherein the isolation film on the substrate is dented at the surface areas corresponding to the wiring region of small wiring-to-wiring distance but not covered by the wirings of the region and the resulting dents are filled with the first inter-level isolation film.  
     
     
         5 . A semiconductor device according to  claim 1 , wherein the first inter-level isolation film is constituted by an organic film, an organic SOG film, a polyimide film, a porous inorganic SOG film having a density smaller than that of silicon oxide film, or a porous organic SOG film, and the second inter-level isolation film is constituted by a silicon oxide film or a silicon oxynitride film.  
     
     
         6 . A semiconductor device according to  claim 2 , wherein the first inter-level isolation film is constituted by an organic film, an organic SOG film, a polyimide film, a porous inorganic SOG film having a density smaller than that of silicon oxide film, or a porous organic SOG film, and the second inter-level isolation film is constituted by a silicon oxide film or a silicon oxynitride film.  
     
     
         7 . A semiconductor device according to  claim 1 , wherein the wirings are formed in a plurality of layer levels so that at each layer level the region in which the wirings are formed is divided into a wiring region of small wiring-to-wiring distance and a wiring region of large wiring-to-wiring distance; a first inter-level isolation film is selectively formed in the wiring region of small wiring-to-wiring distance and a second inter-level isolation film is formed in the wiring region of large wiring-to-wiring distance to cover the wirings; through-holes are formed only in the second inter-level isolation film; and the dielectric constant of the first inter-level isolation film is smaller than the dielectric constant of the second inter-level isolation film.  
     
     
         8 . A semiconductor device according to  claim 2 , wherein the wirings are formed in a plurality of layer levels so that at each layer level the region in which the wirings are formed is divided into a wiring region of small wiring-to-wiring distance and a wiring region of large wiring-to-wiring distance; a first inter-level isolation film is selectively formed in the wiring region of small wiring-to-wiring distance, a second inter-level isolation film is formed in the wiring region of large wiring-to-wiring distance to cover the wirings; and a third inter-level isolation film is formed so as to cover the first inter-level isolation film and the second inter-level isolation film; throughholes are formed only in the second inter-level isolation film and the third inter-level isolation film; and the dielectric constant of the first inter-level isolation film is smaller than the dielectric constants of the second inter-level isolation film and the third inter-level isolation film.  
     
     
         9 . A semiconductor device according to  claim 7 , wherein the isolation film on the substrate is dented at the surface areas corresponding to the wiring region of small wiring-to-wiring distance but not covered by the wirings of the region and the resulting dents are filled with the first inter-level isolation film.  
     
     
         10 . A semiconductor device according to  claim 8 , wherein the isolation film on the substrate is dented at the surface areas corresponding to the wiring region of small wiring-to-wiring distance but not covered by the wirings of the region and the resulting dents are filled with the first inter-level isolation film.  
     
     
         11 . A semiconductor device according to  claim 7 , wherein the first inter-level isolation film is constituted by an organic film, an organic SOG film, a polyimide film, a porous inorganic SOG film having a density smaller than that of silicon oxide film, or a porous organic SOG film, and the second inter-level isolation film is constituted by a silicon oxide film or a silicon oxynitride film.  
     
     
         12 . A semiconductor device according to  claim 8 , wherein the first inter-level isolation film is constituted by an organic film, an organic SOG film, a polyimide film, a porous inorganic SOG film having a density smaller than that of silicon oxide film, or a porous organic SOG film, and the second inter-level isolation film is constituted by a silicon oxide film or a silicon oxynitride film.  
     
     
         13 . A process for producing a semiconductor device, which comprises: 
 a step of forming a plurality of wirings on a semiconductor substrate via an isolation film so that the region in which the wirings are formed is divided into a wiring region of small wiring-to-wiring distance and a wiring region large wiring-to-wiring distance, and forming thereon a first inter-level isolation film so as to cover the wirings and then a protective isolation film in this order,    a step of selectively removing the first inter-level isolation film and the protective isolation film present on and in the wiring region of large wiring-to-wiring distance,    a step of forming, by deposition, depositing a second inter-level isolation film on the whole surface of the resulting material and then subjecting the second inter-level isolation film to chemical mechanical polishing with the protective isolation film used as an etching stopper, to obtain a flat surface, and    a step of forming throughholes only in the second inter-level isolation film.    
     
     
         14 . A process according to  claim 13 , wherein the dielectric constant of the first inter-level isolation film is smaller than the dielectric constant of the second inter-level isolation film and the protective isolation film is more resistant to the chemical mechanical polishing than the second inter-level isolation film.  
     
     
         15 . A process according to  claim 14 , wherein the protective isolation film is constituted by a silicon nitride film, a silicon oxynitride film or a silicon carbide film and the second inter-level isolation film is constituted by a silicon oxide film.  
     
     
         16 . A process for producing a semiconductor device, which comprises: 
 a step of forming a plurality of wirings on a semiconductor substrate via an isolation film so that the region in which the wirings are formed is divided into a wiring region of small wiring-to-wiring distance and a wiring region large wiring-to-wiring distance, and forming thereon a second inter-level isolation film so as to cover the wirings,    a step of selectively removing the second inter-level isolation film present on and in the wiring region of small wiring-to-wiring distance,    a step of forming, by deposition, depositing a first inter-level isolation film on the whole surface of the resulting material, and then subjecting the first inter-level isolation film to chemical mechanical polishing with the second inter-level isolation film used as an etching stopper to obtain a flat surface, and    a step of forming throughholes only in the second inter-level isolation film.    
     
     
         17 . A process according to  claim 16 , wherein the dielectric constant of the first inter-level isolation film is smaller than the dielectric constant of the second inter-level isolation film and the second inter-level isolation film is more resistant to the chemical mechanical polishing than the first inter-level isolation film.  
     
     
         18 . A process according to  claim 17 , wherein the first inter-level isolation film is constituted by an organic film, an organic SOG film, a polyimide film, a porous inorganic SOG film having a density smaller than that of silicon oxide film, or a porous organic SOG film, and the second inter-level isolation film is constituted by a silicon oxide film or a silicon oxynitride film.