Nonvolatile memory device

Abstract

Disclosed herein is a nonvolatile memory device having a plurality of nonvolatile memory cells. In the nonvolatile memory cell, a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side so that each of the memory cells stores information therein. The memory gate electrode and the switch gate electrodes extend in the same direction. Thus, even if a high voltage is applied to the memory gate electrode of each write-intended memory cell which uses the memory gate electrode and switch gate electrodes in common, and write and write blocking voltages are applied through the first and second signal electrodes, each memory cell intended for write non-selection can avoid the application of a high electric field thereto owing to the switch gate electrodes held in a cut-off state.

What is claimed is:  
     
         1 . A method of manufacturing a semiconductor device, comprising the steps of: 
 forming a first conductivity type first semiconductor region on a main surface of a semiconductor substrate;    forming a first insulating film and a second insulating film on the main surface of the semiconductor substrate on the first semiconductor region in order;    forming a first conductor element having a first width as viewed in a first direction of the main surface of the semiconductor substrate and a second width as viewed in a second direction substantially orthogonal to the first direction, on the second insulating film;    introducing a first impurity of the first conductivity type into the first semiconductor region below the first conductor element as viewed in the first direction to selectively form second semiconductor regions;    forming a third insulating film on side walls of the first conductor element as viewed in the first direction;    forming second and third conductor elements respectively having a third width as viewed in the first direction and a fourth width as viewed in the second direction at both ends of the first conductor element as viewed in the first direction with the third insulating film interposed therebetween; and    introducing a second impurity of a second conductivity type opposite to the first conductivity type as viewed in the first direction to form a third semiconductor region within the first semiconductor region on the sides opposite to the first conductor element, of the second and third conductor elements.    
     
     
         2 . The method according to  claim 1 , wherein said second semiconductor region forming step further includes the step of introducing a third impurity of the second conductivity type into the first semiconductor region at both ends of the first conductor element, the third impurity is ion-implanted at a first angle to the main surface of the semiconductor substrate, the first impurity is ion-implanted at a second angle to the main surface of the semiconductor substrate, and the first angle is larger than the second angle.  
     
     
         3 . The method according to  claim 1 , wherein the second width of the first conductor element is greater than the first width, the fourth width of the second conductor element is greater than the third width, and the first and second conductor elements extend in the second direction.  
     
     
         4 . The method according to  claim 1 , wherein the first insulating film comprises silicon oxide, and the second insulating film comprises silicon nitride.  
     
     
         5 . A method of manufacturing a semiconductor device, comprising the steps of: 
 forming a first conductivity type first semiconductor region on a main surface of a semiconductor substrate;    forming two first conductor elements having a first width as viewed in a first direction of the main surface of the semiconductor substrate and a second width as viewed in a second direction substantially orthogonal to the first direction, on the first semiconductor region with a predetermined interval interposed therebetween;    forming a first insulating film on side walls of the first conductor element in a region between the first conductor elements;    introducing a first impurity of the first conductivity type within the first semiconductor region in the region lying between the first conductor elements and interposed by the first insulating film formed on the side walls of the first conductor element in order to form a second semiconductor region there within;    forming a second insulating film and a third insulating film over the surface of the semiconductor substrate in the region between the first conductor elements;    forming a second conductor element having a third width as viewed in the first direction and a fourth width as viewed in the second direction, on the third insulating film; and    introducing a second impurity of a second conductivity type opposite to the first conductivity type as viewed in the first direction to form a third semiconductor region within the first semiconductor region on the side opposite to the second conductor element, of the first conductor element.    
     
     
         6 . The method according to  claim 5 , wherein said first insulating film forming step includes the step of depositing an insulating film on the semiconductor substrate, and the step of subjecting the insulating film to anisotropic etching and selectively leaving the insulating film on the side walls of the first conductor element.  
     
     
         7 . The method according to  claim 5 , wherein the second conductor element is formed on the side walls of the first conductor element with the third insulating film interposed therebetween.  
     
     
         8 . The method according to  claim 7 , wherein the second insulating film comprises silicon oxide, and the third insulating film comprises silicon nitride.  
     
     
         9 . The method according to  claim 5 , wherein the second width of the first conductor element is greater than the first width, the fourth width of the second conductor element is greater than the third width, and the first and second conductor elements extend in the second direction.