Semiconductor device

Abstract

A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements being arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on the insulator substrate.

What is claimed is:  
     
         1 . A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of said semiconductor element being electrically connected to said electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of said heat dissipating base being covered with a member for cutting off said semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside said cutoff member being provided, wherein the material of said heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK; said semiconductor elements being arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on said insulator substrate.  
     
     
         2 . A semiconductor device according to  claim 1 , wherein said plurality of semiconductor elements, the main surface of said insulator substrate and the upper surface of said heat dissipating base are coated with a gelatin, the surface of said gelatin being substantially exposed to a space inside said cutoff member.  
     
     
         3 . A semiconductor device according to  claim 1 , wherein a space is provided between the electrode pattern portion connected with said electrode terminals on the insulator substrate and said insulator substrate, a metallic patter being formed on the side of the insulator substrate so as to include the projecting area of said space to said insulator substrate, said metallic pattern being in the same electrical potential as said electrode pattern.  
     
     
         4 . A semiconductor device according to  claim 1 , wherein said insulator substrate comprises on the substrate at least one inter-layer electrode pattern without exposing the end surface having the same electrical potential as the main current electrode pattern formed on the main surface of the substrate.  
     
     
         5 . A semiconductor device according to  claim 1 , wherein an interposing member having a linear expansion coefficient near the linear expansion coefficient of the heat dissipating base is inserted between the main current electrode and the electrode on the insulator substrate corresponding to the main current electrode.  
     
     
         6 . A semiconductor device according to  claim 1 , wherein in at least one of the terminals the distance between the end of the terminal connected with said electrode terminal and the end of the electrode pattern on the insulator substrate corresponding to said terminal is substantially larger than twice of the sum of the thickness of the member constructing the terminal and the thickness of said electrode pattern.  
     
     
         7 . A semiconductor device according to  claim 1 , wherein the main external electrodes are arranged parallel to the direction of the shorter side of the semiconductor device.  
     
     
         8 . A semiconductor device according to  claim 1 , wherein a collar made of a material having a linear expansion coefficient substantially equal to the linear expansion coefficient of the fixing bolt for attaching said device to an external cooling plate is attached to a hole for attaching said device to the external cooling plate.  
     
     
         9 . A semiconductor device according to  claim 1 , wherein two of the main current terminals are arranged within the gelatin in crossing to each other and spacing in the height direction, the raising portions from the inside of the gelatin to the external electrodes being in parallel to each other.  
     
     
         10 . A semiconductor device according to  claim 1 , wherein an auxiliary terminal for connecting a resistor is provided in the input terminal.  
     
     
         11 . A semiconductor device according to  claim 2 , wherein the terminals in the space above the surface of said gelatin are covered with a material equivalent to the material making said cutoff member.  
     
     
         12 . A semiconductor device according to  claim 2 , wherein the members composing said terminals and another of said cutoff member are bonded with a hard resin.  
     
     
         13 . A semiconductor device according to  claim 2 , wherein said cutoff member and the terminals are molded as a unit or bonded with a hard resin.  
     
     
         14 . A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of said semiconductor element being electrically connected to said electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of said heat dissipating base being covered with a member for cutting off said semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside said cutoff member being provided, wherein said semiconductor elements are arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on said insulator substrate, at least the semiconductor elements, the main surface of said insulator substrate and the surface of the heat dissipating base being coated with a gelatin, the surface of said gelatin being substantially exposed to a space inside said cutoff member.  
     
     
         15 . A semiconductor device according to  claim 14 , wherein a space is provided between the electrode pattern portion connected with said electrode terminals on the insulator substrate and said insulator substrate, a metallic patter being formed on the side of the insulator substrate so as to include the projecting area of said space to said insulator substrate, said metallic pattern being in the same electrical potential as said electrode pattern.  
     
     
         16 . A semiconductor device according to  claim 14 , wherein said insulator substrate comprises on the substrate at least one inter-layer electrode pattern without exposing the end surface having the same electrical potential as the main current electrode pattern formed on the main surface of the substrate.  
     
     
         17 . A semiconductor device according to  claim 14 , wherein in at least one of the terminals the distance between the end of the terminal connected with said electrode terminal and the end of the electrode pattern on the insulator substrate corresponding to said terminal is substantially larger than twice of the sum of the thickness of the member constructing the terminal and the thickness of said electrode pattern.  
     
     
         18 . A semiconductor device according to  claim 14 , wherein the main external electrodes are arranged parallel to the direction of the shorter side of the semiconductor device.  
     
     
         19 . A semiconductor device according to  claim 14 , wherein two of the main current terminals are arranged within the gelatin in crossing to each other and spacing in the height direction, the raising portions from the inside of the gelatin to the external electrodes being in parallel to each other.  
     
     
         20 . A semiconductor device according to  claim 14 , wherein an auxiliary terminal for connecting a resistor is provided in the input terminal.  
     
     
         21 . A semiconductor device according to  claim 14 , wherein the terminals in the space above the surface of said gelatin are covered with a material equivalent to the material making said cutoff member.  
     
     
         22 . A semiconductor device according to  claim 14 , wherein the members composing said terminals and another of said cutoff member are bonded with a hard resin.  
     
     
         23 . A semiconductor device according to  claim 14 , wherein said cutoff member and the terminals are molded as a unit or bonded with a hard resin.  
     
     
         24 . An inverter device for electric power using the semiconductor device according to  claim 1 .  
     
     
         25 . A circuit board comprising: 
 an insulator plate;    a first conductor layer provided on one of the surfaces of the insulator plate;    a second conductor layer provided in a position facing to the first conductor layer on the insulator plate; and    a conductor electrically connecting the first conductor layer and the second conductor layer.    
     
     
         26 . A circuit board according to  claim 25 , which comprises a dielectric interposed between said first conductor layer and said second conductor layer.  
     
     
         27 . A circuit board according to  claim 25 , wherein the position of the end portion of said second conductor layer is at the position of the end portion of said first conductor layer or at the position between the end portion of said first conductor layer and the end portion of said insulator plate.  
     
     
         28 . A circuit board according to  claim 25 , wherein said second conductor layer comprises a layer selected from the group consisting of a metallized layer of tungsten, a metallized layer of molybdenum and manganese, a layer plated over a metallized layer of tungsten, a layer plated over a metallized layer of molybdenum and manganese.  
     
     
         29 . A circuit board comprising: 
 an insulator plate;    a first conductor layer provided on one of the surfaces of the insulator plate;    a second conductor layer provided in separating from the first conductor layer on the insulator plate; and    a conductor electrically connecting the first conductor layer and the second conductor layer.    
     
     
         30 . A circuit board comprising: 
 an insulator plate;    a conductor layer placed on the surface of the insulator plate;    a dielectric layer provided in a gap portion between the insulator plate and the conductor layer; wherein    the following relationship exists among the dielectric constant of the dielectric layer ∈ g , the dielectric constant of the insulator plate ∈ b , the thickness of the gap portion L g , and the thickness of the insulator plate L b , ∈ g ≧∈ b ×(L g /L b ).    
     
     
         31 . A semiconductor module mounting a plurality of semiconductor elements of the same kind, which comprises: 
 a substrate made of an insulator;    said plurality of semiconductor elements arranged on said insulator substrate;    external connecting terminals electrically connected to an external apparatus;    a conductor pattern formed on said insulator substrate, jointed with said external connecting terminals as well as electrically connected with the electrodes of said plurality of semiconductor elements in parallel to form a current path from said external connecting terminals to said plurality of semiconductor elements; wherein    said conductor pattern is formed symmetrically in regard to a certain phantom line on said insulator substrate, a plurality of positions on said phantom line and symmetrical in regard to said phantom line being used as jointing zones for said external connecting terminal, current bypass portions to make the individual current paths of said plurality of semiconductor elements in a nearly equal length being provided, the current bypass portion being formed by cutting away a path between a semiconductor element and said jointing zone and providing a bypass for allowing current to flow between the semiconductor element and said jointing zone when the distance between the electrode of the semiconductor element and said jointing zone is shorter than the distances between the electrodes of the other semiconductor elements and said jointing zones (in a case where the semiconductor element has plural electrodes or an expanded electrode the averaged distance being taken as said distance between the electrode of the semiconductor element and said jointing zone.)    
     
     
         32 . A semiconductor module according to  claim 31 , wherein three of said semiconductor elements of the same kind are mounted, one special semiconductor element among said three semiconductor elements being arranged so that the center of weight is placed on said phantom line, the other two semiconductor elements being arranged so that the centers of weight each are placed symmetrically each other in regard to said phantom line and at the corners each in the base of an isosceles triangle having the center of weight of said special semiconductor element as the vertex.  
     
     
         33 . A semiconductor module mounting a plurality of semiconductor elements of the same kind, which comprises: 
 a substrate made of an insulator;    said plurality of semiconductor elements arranged on said insulator substrate;    external connecting terminals electrically connected to an external apparatus;    a conductor pattern formed on said insulator substrate, jointed with said external connecting terminals as well as electrically connected with the electrodes of said plurality of semiconductor elements in parallel to form a current path from said external connecting terminals to said plurality of semiconductor elements; wherein    said external connecting terminal comprises a facing portion on said conductor pattern, the facing portion being parallel to and facing to the zone of each of the current paths for each of said semiconductor elements, the direction of current flow in the facing portion being opposite to the direction of current flow in each of the current paths.    
     
     
         34 . A semiconductor module according to  claim 33 , wherein 
 said plurality of semiconductor elements are arranged in a straight line on said substrate,    said conductor pattern being formed in the interval from the semiconductor element in one end among said plurality of semiconductor elements arranged in a straight line to the semiconductor element in the other end along said plurality of semiconductor elements,    said external connecting terminal being jointed to the portion in the side of said semiconductor element in one end of said conductor pattern, said facing portion extending in the direction arranging said plurality of semiconductor elements from a position corresponding to the position of said semiconductor element in one end to a position corresponding to the position of said semiconductor element in the other end.    
     
     
         35 . A semiconductor module according to  claim 31 , wherein 
 each of said plurality of semiconductor elements individually has an input electrode for allowing current to flow into and an output electrode for allowing current to flow out as said electrodes,    an input side connecting terminal for allowing current to flow into from an external apparatus and an output side connecting terminal for allowing current to flow out being provided as said external connecting terminals,    an input side conductor pattern jointed with said input side connecting terminal and electrically connected with the input electrodes of said plurality of semiconductor elements in parallel and an output side conductor pattern jointed with said output side connecting terminal and electrically connected with the output electrodes of said plurality of semiconductor elements in parallel being provided as said conductor pattern, said input side connecting terminal and said output side terminal being faced to each other with a space, having parallel input/output facing portions.    
     
     
         36 . A semiconductor module according to  claim 35 , wherein the gap between said input/output facing portions of said input side connecting terminal and said input/output facing portions of said output side connecting terminal is shorter than 10 mm.  
     
     
         37 . A semiconductor module according to  claim 31 , wherein said plurality of semiconductor elements are bipolar transistors, each of the semiconductor element having an input electrode for allowing current to flow into and an output electrode for allowing current to flow out as said electrodes and a control electrode for applying voltage for controlling the quantity of current flowing from said input electrode to said output electrode, 
 an input side connecting terminal for allowing current to flow into from an external apparatus and an output side connecting terminal for allowing current to flow out and a control connecting terminal for applying voltage from an external apparatus being provided as said external connecting terminals,    an input side conductor pattern jointed with said input side connecting terminal and electrically connected with the input electrodes of said plurality of semiconductor elements in parallel and an output side conductor pattern jointed with said output side connecting terminal and electrically connected with the output electrodes of said plurality of semiconductor elements in parallel and a control conductor pattern jointed with said control connecting terminal and electrically connected with said control electrodes of said plurality of semiconductor elements in parallel being provided as said conductor pattern,    said control connecting terminal being formed and arranged so that the control connecting terminal does not cross with said input side connecting terminal and said output side connecting terminal, and the distance from said control connecting terminal to said input side connecting terminal and said output side connecting terminal is longer than the distance between said input side connecting terminal and said output side connecting terminal.    
     
     
         38 . A semiconductor module according to  claim 37 , wherein 
 a diode element having an input electrode for allowing current to flow into and an output electrode for allowing current to flow out is provided,    the input electrode of said diode element being electrically connected with said input side conductor pattern, the output electrode of said diode element being electrically connected with said output side conductor pattern,    the jointing zone of said input side connecting terminal on said input side conductor pattern being placed at a position where the length of the current path from said jointing zone to the input electrode of said diode element is shorter than the length of the current path from said jointing zone to said input electrode of said bipolar transistor.    
     
     
         39 . A semiconductor module according to  claim 31 , wherein said external connecting terminal has a bending portion at which the extension of said external connecting terminal in a certain direction turns to the extension of said external connecting terminal in the direction opposite to said certain direction.  
     
     
         40 . A semiconductor module according to  claim 39 , which comprises 
 a metallic wire connecting said conductor pattern and the electrode of said semiconductor element,    said bending portion of said external connecting terminal being formed so as not to be placed over/under said metallic wire.    
     
     
         41 . A semiconductor module according to  claim 31 , which comprises 
 a casing for covering said insulator substrate so that a space is formed in the arranging side of said semiconductor element and said conductor pattern on said insulator substrate,    silicone gel for filling said space of said casing,    said silicone gel filling said space so that an air layer is formed inside said space of said casing.