Microstructure control of copper interconnects

Abstract

A method and structure is described which substantially eliminates the grain growth of copper due to self annealing. Basically, by alloying the copper interconnect e.g. with Cr, Co, Zn or Ag in an amount which does not cause a second phase or precipitation at the annealing temperature, one can control and maintain the grain size of the copper and hence achieve a uniform microstructure while improving the strength, hardness and CMP removal rate of the interconnect while substantially maintaining the conductivity of the copper.

What is claimed is:  
     
         1 . An integrated circuit device having copper interconnects said interconnects having one or more alloying elements therein which elements substantially prevent grain growth of the copper due to self annealing.  
     
     
         2 . The device recited in  claim 1  wherein the alloying elements comprise at least one member of the group consisting of Cr, Co, Zn and Ag.  
     
     
         3 . The device recited in  claim 1  wherein the alloying elements are present in an amount less than the solubility limit of the elements in copper at the annealing temperature employed to disperse said elements in the copper.  
     
     
         4 . The device recited in  claim 1  wherein the alloying elements do not create a second phase or precipitate within the alloy.  
     
     
         5 . The device recited in  claim 4  wherein the alloying elements do not comprise more than 0.5 wt % of the copper.  
     
     
         6 . The device recited in  claim 1  further comprising a Si substrate, a dielectric layer over at least a portion of said substrate and having a trench, via, damascene or dual damascene structure therein, a Cu migration barrier layer in said trench, via or damascene structure, a Cu seed layer over said barrier layer and wherein said copper interconnect is electrodeposited to essentially fill the remainder of the trench, via or damascene structure.  
     
     
         7 . The device recited in  claim 6  wherein the dielectric layer is selected from the group consisting of silicon dioxide, tantalum oxide, a low k dielectric, a xerogel and an aerogel.  
     
     
         8 . The device recited in  claim 6  wherein the barrier layer is from 25-500 angstroms thick and the copper seed layer is from 25-2,000 angstroms thick.  
     
     
         9 . A method of forming an integrated circuit device having copper interconnects which are not prone to grain growth due to self annealing comprising alloying the copper of the interconnect with one or more elements which can control and maintain the grain size and grain boundaries of the copper without significant loss of conductivity, including the step of annealing, wherein the alloying elements are present in an amount less than that which creates a second copper phase or precipitate within the alloy at the annealing temperature.  
     
     
         10 . The method recited in  claim 9  wherein the device structure comprises a Si substrate, a dielectric layer over at least a portion of said substrate and having a trench, via, damascene or dual damascene structure therein, a Cu migration barrier layer in said trench, via or damascene structure, a Cu seed layer over said barrier layer and wherein said copper interconnect is electrodeposited to essentially fill the remainder of the trench, via or damascene structure and wherein alloying of the copper is accomplished by introducing the alloying elements to at least one of the following; the barrier layer, the seed layer; and the copper interconnect, and then annealing the device to diffuse the alloying element throughout the copper interconnect.  
     
     
         11 . The method recited in  claim 10  wherein the alloying elements comprise at least one member of the group consisting of Cr, Co, Zn and Ag.  
     
     
         12 . The method recited in  claim 10  wherein the alloying element is incorporated into the seed layer during formation of that layer by a PVD or CVD process.  
     
     
         13 . The method recited in  claim 12  wherein the seed layer is from 25-2,000 Å thick.  
     
     
         14 . The method recited in  claim 10  wherein the seed layer is formed by forming alternate layers of copper and alloying element.  
     
     
         15 . The method recited in  claim 9  wherein annealing is at a temperature of from 100° C.-400° C. for 1-3 hours in a reducing or inert atmosphere.