Semiconductor wafer, semiconductor chip, semiconductor device and method for manufacturing semiconductor device

Abstract

There is provided an electrical characteristic test technique for a semiconductor device that can shorten the time required for a next probe test after a wafer level burn-in test, prevent leak of defective product to an assembling process and moreover easily realizes the analysis of cause for generation of a fault after delivery of products to customers. In this electrical characteristic test technique, a multi-chip package MCP mounts a couple of semiconductor chips of flash memory and SRAM, a simultaneous contact check is executed for an input/output pad of each semiconductor chip and an erase/write mode and a read mode are respectively executed for a memory array of each semiconductor chip depending on the steps S 201 to S 211 on the occasion of conducting the wafer level burn-in of the semiconductor chip of flash memory, historical data of these test results is written into the semiconductor chip of flash memory and the historical data written in the wafer level burn-in process is read in a next probe test process and the probe test is continuously implemented only to the semiconductor chip of a good product.

What is claimed is:  
     
         1 . A semiconductor wafer comprising: 
 a plurality of semiconductor chips each of which also includes a non-volatile memory array,    wherein said plurality of semiconductor chips each comprises: 
 a first memory area for storing input information of usual operation; and  
 a second memory area for storing historical information of an electric characteristic test of said first memory area.  
   
     
     
         2 . A semiconductor wafer according to  claim 1 , wherein said electrical characteristic test is a wafer level burn-in test.  
     
     
         3 . A semiconductor wafer according to  claim 2 , wherein said second memory area is a flash fuse area of said non-volatile memory area.  
     
     
         4 . A semiconductor wafer according to  claim 2 , wherein said second memory area is an OTP area of said non-volatile memory area.  
     
     
         5 . A semiconductor wafer according to  claim 2 , wherein said second memory area is a lock bit area of said non-volatile memory area.  
     
     
         6 . A semiconductor wafer according to  claim 2 , wherein said second memory area is a part of said first memory area of said non-volatile memory area.  
     
     
         7 . A semiconductor chip including a non-volatile memory array, comprising: 
 a first memory area for storing input information of usual operation; and    a second memory area for storing historical information of an electrical characteristic test of said first memory area.    
     
     
         8 . A semiconductor chip according to  claim 7 , wherein said electrical characteristic test is a wafer level burn-in test.  
     
     
         9 . A semiconductor device mounting a semiconductor chip including a non-volatile memory array, said non-volatile memory array comprising: 
 a first memory area for storing input information of usual operation; and    a second memory area for storing historical information of an electrical characteristic test of said first memory area.    
     
     
         10 . A semiconductor device according to  claim 9 , 
 wherein said electrical characteristic test is a wafer level burn-in test.    
     
     
         11 . A semiconductor device comprising: 
 a first semiconductor chip including a non-volatile memory array comprising: 
 a first memory area for storing input information of usual operation, and  
 a second memory area for storing historical information of an electrical characteristic test of said first memory area; and  
   a second semiconductor chip including a volatile memory array comprising a third memory area for storing input information of usual operation,    wherein historical information of an electrical characteristic test of said third memory area of said second semiconductor chip is stored into said second memory area of said first semiconductor chip.    
     
     
         12 . A semiconductor device according to  claim 11 , wherein said electrical characteristic test is the wafer level burn-in test.  
     
     
         13 . A method of manufacturing a semiconductor device including a semiconductor chip having a non-volatile memory array cut out from a semiconductor wafer, the method comprising: 
 conducting an electrical characteristic test of a first memory area for storing input information of usual operation of said semiconductor chip before cutting out said semiconductor chip from said semiconductor wafer; and    storing said historical information of said electrical characteristic test to the second memory area of said semiconductor chip.    
     
     
         14 . A method of manufacturing a semiconductor device according to  claim 13 , wherein said electrical characteristic test is a wafer level burn-in test.  
     
     
         15 . A method of manufacturing a semiconductor device according to  claim 14 , wherein historical information of said second memory area is temporarily saved, at the time of conducting the wafer level burn-in test, to a testing apparatus before starting said wafer level burn-in test, and wherein this historical information is combined, after the wafer level burn-in test, with the historical information before the test and the combined historical information is then stored in said second memory area.  
     
     
         16 . A method of manufacturing a semiconductor device including a first semiconductor chip having a nonvolatile memory array cut out from the semiconductor wafer and a second semiconductor chip having a volatile memory array, comprising the steps of: 
 conducting an electrical characteristic test of a first memory area for storing input information of usual operation of said first semiconductor chip before cutting out said semiconductor chip from said semiconductor wafer;    storing historical information of an electrical characteristic test of said first memory area of said first semiconductor chip to the second memory area of said first semiconductor chip;    conducting an electrical characteristic test of the third memory area for storing input information of usual operation of said second semiconductor chip before cutting out said semiconductor chip from said semiconductor wafer; and    storing historical information of an electrical characteristic test of said third memory area of said second semiconductor chip to said second memory area of said first semiconductor chip.    
     
     
         17 . A method of manufacturing a semiconductor device according to  claim 16 , wherein said electrical characteristic test is a wafer level burn-in test.  
     
     
         18 . A method of manufacturing a semiconductor device according to  claim 17 , wherein the historical data of said second memory area of said first semiconductor chip is temporarily saved, at the time of conducting the wafer level burn-in test, to a testing apparatus before starting said test, and wherein this historical information is combined, after this test, with the historical information before the test to store the combined historical information to said second memory area of said first semiconductor chip.