Voltage regulator and data path for a memory device

Abstract

One aspect of the present invention is directed to a method and apparatus of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, with the gate voltages being supplied by a voltage regulator through an output bus to a plurality of output blocks. The demand for gate voltage is periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. In addition, additional current is temporarily sourced to the output terminal of the voltage regulator. Another aspect of the present invention is directed to a method and apparatus of producing a control pulse of an extended duration for use in the voltage regulator. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration. A plurality of delay circuits receives the control pulse and produces a plurality of delayed control pulses. A second logic gate receives the control pulse and the plurality of delayed control pulses and produces a control pulse of extended duration. The control pulse of extended duration may be used, for example, for temporarily sourcing additional current to an output terminal of the voltage regulator. According to another aspect of the present invention, a method is disclosed of forcing a voltage regulator into a low power mode. Another aspect of the present invention is directed to a pre-driver or the like which provides variable output drive capability. The pre-driver is comprised of two paths each divided into output stages. A signal is generated in response to determining the relative strength of the n-channel and p-channel transistors in a subsequent output amplifier. The signal is then used to enable certain of the output stages in each of the output paths.

What is claimed is:  
     
         1 . A method of boosting the voltage supplied to an output pad driver through a bus connected to a voltage regulator, comprising: 
 momentarily connecting the bus to a voltage source; and    temporarily sourcing additional current to the output terminal of the voltage regulator.    
     
     
         2 . The method of  claim 1  additionally comprising generating a one-shot control pulse, and wherein said one-shot control pulse initiates the momentarily connecting step.  
     
     
         3 . The method of  claim 1  additionally comprising generating a temporary control pulse, and wherein said temporary control pulse initiates the temporarily sourcing step.  
     
     
         4 . A method of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, said gate voltages supplied by a voltage regulator through an output bus, comprising: 
 periodically determining the demand for gate voltage and, when the demand is high,    momentarily connecting each line of the bus to a voltage source; and    temporarily sourcing additional current to the output terminal of the voltage regulator.    
     
     
         5 . The method of  claim 4  additionally comprising generating a one-shot control pulse, and wherein said one-shot control pulse initiates the momentarily connecting step.  
     
     
         6 . The method of  claim 4  additionally comprising generating a temporary control pulse, and wherein said temporary control pulse initiates the temporarily sourcing step.  
     
     
         7 . A booster circuit for use with a voltage regulator, having an output terminal coupled with a voltage bus, said voltage bus servicing a plurality of output blocks through a plurality of output lines, said booster circuit comprising: 
 a plurality of switches for connecting each output line of the voltage bus to a voltage source; and    a switching circuit for sourcing additional current to the output terminal of the voltage regulator.    
     
     
         8 . The booster circuit of  claim 7  wherein said plurality of switches includes a plurality of transistors.  
     
     
         9 . The booster circuit of  claim 7  wherein said switching circuit includes a transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said transistor.  
     
     
         10 . A booster circuit for use with a voltage regulator, having an output terminal coupled with a voltage bus, said voltage bus servicing a plurality of output blocks through a plurality of output lines, said booster circuit comprising: 
 a plurality of switches for connecting each output line of the voltage bus to a voltage source; and    a first switching circuit for sourcing additional current to the output terminal of the voltage regulator; and    a second switching circuit for sourcing additional current to the output terminal of the voltage regulator.    
     
     
         11 . The booster circuit of  claim 10  wherein said plurality of switches includes a plurality of transistors.  
     
     
         12 . The booster circuit of  claim 10  wherein said first switching circuit includes a p-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said p-channel transistor and wherein said second switching circuit includes an n-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said n-channel transistor.  
     
     
         13 . A combination, comprising: 
 a plurality of data pads;    a plurality of output blocks each servicing one of said data pads;    a voltage regulator;    a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks;    a plurality of switches for connecting each line of the voltage bus to a voltage source; and    a switching circuit for sourcing additional current to the output terminal of the voltage regulator.    
     
     
         14 . The combination of  claim 13  wherein said plurality of switches includes a plurality of transistors.  
     
     
         15 . The combination of  claim 13  wherein said switching circuit includes a transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said transistor.  
     
     
         16 . A combination, comprising: 
 a plurality of data pads;    a plurality of output blocks each servicing one of said data pads;    a voltage regulator;    a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks;    a plurality of switches for connecting each line of the voltage bus to a voltage source;    a first switching circuit for sourcing additional current to the output terminal of the voltage regulator; and    a second switching circuit for sourcing additional current to the output terminal of the voltage regulator.    
     
     
         17 . The combination of  claim 16  wherein said plurality of switches includes a plurality of transistors.  
     
     
         18 . The combination of  claim 16  wherein said first switching circuit includes a p-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said p-channel transistor and wherein said second switching circuit includes an n-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said n-channel transistor.  
     
     
         19 . A memory device, comprising: 
 a plurality of memory cells arranged in an array of rows and columns;    a plurality of devices for identifying cells within said array;    a plurality of pads;    a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;    a voltage regulator;    a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks;    a plurality of switches for connecting each line of the voltage bus to a voltage source; and    a switching circuit for sourcing additional current to an output terminal of said voltage regulator.    
     
     
         20 . The memory device of  claim 19  wherein said plurality of switches includes a plurality of transistors.  
     
     
         21 . The memory device of  claim 19  wherein said switching circuit includes a transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said transistor.  
     
     
         22 . A memory device, comprising: 
 a plurality of memory cells arranged in an array of rows and columns;    a plurality of devices for identifying cells within said array;    a plurality of pads;    a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;    a voltage regulator;    a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks;    a plurality of switches for connecting each line of the voltage bus to a voltage source;    a first switching circuit for sourcing additional current to the output terminal of the voltage regulator; and    a second switching circuit for sourcing additional current to the output terminal of the voltage regulator.    
     
     
         23 . The memory device of  claim 22  wherein said plurality of switches includes a plurality of transistors.  
     
     
         24 . The memory device of  claim 22  wherein said first switching circuit includes a p-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said p-channel transistor and wherein said second switching circuit includes an n-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said n-channel transistor.  
     
     
         25 . A method of extending the duration of a control pulse, comprising: 
 inputting the control pulse to a logic gate;    delaying the control pulse by a plurality of delay periods to produce a plurality of delayed control pulses; and    inputting said delayed control pulses to said logic gate, wherein a control pulse of extended duration is available at an output of said logic gate.    
     
     
         26 . A method of producing a control pulse of extended duration, comprising: 
 inputting a plurality of signals to a first logic gate to produce a control pulse of a first duration;    inputting the control pulse to a second logic gate;    inputting the control pulse to a plurality of delay circuits to produce a plurality of control pulses having varying amounts of delay; and    inputting said delayed control pulses to said second logic gate to produce a control pulse of extended duration.    
     
     
         27 . The method of  claim 26  wherein said step of inputting a plurality of signals to a first logic gate includes the step of inputting a plurality of one-shot control pulses representative of demand.  
     
     
         28 . The method of  claim 26  additionally comprising the step of using said control pulse of extended duration to control the period of conduction of a transistor.  
     
     
         29 . A circuit for producing a control pulse of extended duration, comprising: 
 a first logic gate for receiving each of a plurality of signals and for producing a control pulse of a first duration;    a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and    a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.    
     
     
         30 . A circuit for producing a control pulse of extended duration, said circuit for a voltage regulator having an output terminal coupled with a voltage bus, said voltage bus servicing a plurality of output blocks through a plurality of output lines, said circuit comprising: 
 a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration;    a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and;    a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.    
     
     
         31 . A combination, comprising: 
 a plurality of data pads;    a plurality of output blocks each servicing one of said data pads;    a voltage regulator;    a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks;    a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration;    a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and    a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing a control pulse of extended duration, said control pulse input to said voltage regulator.    
     
     
         32 . A memory device, comprising: 
 a plurality of memory cells arranged in an array of rows and columns;    a plurality of devices for identifying cells within said array;    a plurality of pads;    a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;    a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof;    a transistor connected between a voltage source and the output terminal of said voltage regulator; and    a circuit for producing a control pulse of extended duration for input to said transistor, said circuit comprising: 
 a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration;  
 a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and  
 a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.  
   
     
     
         33 . A memory device, comprising: 
 a plurality of memory cells arranged in an array of rows and columns;    a plurality of devices for identifying cells within said array;    a plurality of pads;    a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;    a voltage bus;    a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof through said bus;    a plurality of switches for connecting each line of the voltage bus to a voltage source;    a switching circuit for sourcing additional current to an output terminal of said voltage regulator; and    a circuit for producing a control pulse of extended duration for input to said switching circuit, said circuit comprising: 
 a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration;  
 a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and  
 a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.  
   
     
     
         34 . A memory device, comprising: 
 a plurality of memory cells arranged in an array of rows and columns;    a plurality of devices for identifying cells within said array;    a plurality of pads;    a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;    a voltage bus;    a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof through said bus;    a plurality of switches for connecting each line of the voltage bus to a voltage source;    a first switching circuit including a p-channel device for sourcing additional current to an output terminal of said voltage regulator;    a second switching circuit including an n-channel transistor for sourcing additional current to an output terminal of said voltage regulator; and    a circuit for producing a control pulse of extended duration for input to said first and second switching circuits, said circuit comprising: 
 a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration;  
 a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and  
 a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.  
   
     
     
         35 . A method of forcing a voltage regulator of the type having an amplifier and an output transistor responsive to the amplifier into a low power mode, comprising: 
 temporarily increasing the rate at which a bias current supplied to the differential amplifier is decreased; and    pulling a load connected to the output transistor to a predetermined voltage other than ground.    
     
     
         36 . The method of  claim 35  wherein said step of temporarily increasing includes the step of temporarily grounding through a diode the line carrying a signal for controlling the bias current.  
     
     
         37 . The method of  claim 35  wherein said step of pulling to a predetermined voltage includes the step of pulling to a system voltage less the voltage drop across a diode.  
     
     
         38 . A method, comprising: 
 controlling a pair of output transistors with a differential amplifier;    temporarily increasing the rate at which a bias voltage is withdrawn from the differential amplifier; and    pulling a node between a resistive and capacitive load connected to one of the transistors to a predetermined voltage other than ground.    
     
     
         39 . The method of  claim 38  wherein said step of temporarily increasing includes the step of temporarily grounding through a diode the line carrying a signal for controlling the bias current.  
     
     
         40 . The method of  claim 38  wherein said step of pulling to a predetermined voltage includes the step of pulling to a system voltage less the voltage drop across a diode.  
     
     
         41 . A method, comprising: 
 controlling an output transistor with a signal produced by an amplifier;    producing a control pulse;    temporarily grounding a signal for controlling the bias voltage applied to the amplifier when the amplifier is to enter a low power mode of operation in response to said control pulse; and.    pulling a node between a resistive and capacitive load connected to the transistor to a predetermined voltage other than ground in response to said control pulse.    
     
     
         42 . The method of  claim 41  wherein said temporarily grounding and pulling steps are performed simultaneously.  
     
     
         43 . An apparatus for forcing a voltage regulator of the type having an amplifier controlling an output transistor into a low power mode, comprising: 
 a first switch for connecting a control signal for controlling a source of bias voltage for the amplifier to ground; and    a second switch connected between a resistive and capacitive load connected to the output transistor and a predetermined voltage other than ground.    
     
     
         44 . The apparatus of  claim 43  wherein said second switch is connected to said predetermined voltage through a diode.  
     
     
         45 . A voltage regulator, comprising: 
 first and second output transistors;    an amplifier producing first and second output signals for controlling said first and second transistors, respectively;    a resistive and capacitive load connected across said first output transistor;    a circuit for providing a bias voltage to said amplifier in response to a control signal;    a first switch for connecting said control signal to ground; and    a second switch connected between said load and a predetermined voltage other than ground.    
     
     
         46 . A memory device, comprising: 
 a plurality of memory cells arranged in an array of rows and columns;    a plurality of devices for identifying cells within said array;    a plurality of pads;    a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;    a voltage regulator;    a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks,    said voltage regulator comprising: 
 first and second output transistors;  
 an amplifier producing first and second output signals for controlling said first and second transistors, respectively;  
 a resistive and capacitive load connected across said first output transistor;  
 a circuit for providing a bias voltage to said amplifier in response to a control signal;  
 a first switch for connecting said control signal to ground; and  
 a second switch connected between said load and a predetermined voltage other than ground.  
   
     
     
         47 . A method of providing variable output drive capability to correct for output skews in subsequent amplification stages, comprising: 
 providing a plurality of output drive stages;    controlling the number of output drive stages that are activated in response to the amount of skew.    
     
     
         48 . The method of  claim 47  wherein said step of controlling includes the step of generating a two-bit code and wherein said two-bit code is used to control the number of active output drive stages.  
     
     
         49 . A method of providing variable output drive capability, comprising: 
 generating a two-bit signal representative of the relative strength of the n-channel and p-channel transistors in an output device; and    controlling the number of output pre-driver stages that are active in response to said two-bit signal.    
     
     
         50 . A method, comprising: 
 generating a signal representative of the relative strength of the n-channel and p-channel transistors in an output device;    enabling certain output stages in a pre-driver in response to said signal; and    inputting a high and a low data signal to the output device through the pre-driver.    
     
     
         51 . The method of  claim 50  wherein said enabling step reduces skew in the data output by the output device.  
     
     
         52 . A pre-driver providing variable output drive capability, comprising: 
 a plurality of output transistors; and    a plurality of switches for controlling the conductivity of said plurality of output transistors in response to signals indicative of the strength of the output transistors in an output device.    
     
     
         53 . A pre-driver having an unbalanced output, comprising: 
 a plurality of transistor output stages; and    a plurality of switches for controlling the conductivity of said plurality of output stages in response to the level of conductivity of a subsequent output stage.    
     
     
         54 . A portion of a data path, comprising: 
 an output driver responsive to a data signal; and    a pre-driver providing variable output drive capability, comprising: 
 a plurality of output transistors; and  
 a plurality of switches for controlling the conductivity of said plurality of output transistors in response to signals indicative of the strength of output transistors in said output driver, said pre-driver for providing said data signal to said output driver.  
   
     
     
         55 . A memory device, comprising: 
 a plurality of memory cells arranged in an array of rows and columns;    a plurality of devices for identifying cells within said array;    a plurality of pads;    a data path connecting said plurality of pads and said array, said data path including 
 an output driver responsive to a data signal; and  
 a pre-driver providing variable output drive capability, comprising: 
 a plurality of output transistors; and  
 a plurality of switches for controlling the conductivity of said plurality of output transistors in response to signals indicative of the strength of output transistors in said output driver, said pre-driver for providing said data signal to said output driver.  
 
   
     
     
         56 . A computer system, comprising: 
 a processor having a processor bus;    an input device coupled to the processor through the processor bus;    an output device coupled to the processor through the processor bus;    a memory device coupled to the processor bus, the memory device comprising: 
 a plurality of memory cells arranged in an array of rows and columns;  
 a plurality of devices for identifying cells within said array;  
 a plurality of pads;  
 a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;  
 a voltage regulator;  
 a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks;  
 a plurality of switches for connecting each line of the voltage bus to a voltage source; and  
 a switching circuit for sourcing additional current to an output terminal of said voltage regulator.  
   
     
     
         57 . A computer system, comprising: 
 a processor having a processor bus;    an input device coupled to the processor through the processor bus;    an output device coupled to the processor through the processor bus;    a memory device coupled to the processor bus, the memory device comprising: 
 a plurality of memory cells arranged in an array of rows and columns;  
 a plurality of devices for identifying cells within said array;  
 a plurality of pads;  
 a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;  
 a voltage regulator;  
 a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks;  
 a plurality of switches for connecting each line of the voltage bus to a voltage source;  
 a first switching circuit for sourcing additional current to the output terminal of the voltage regulator; and  
 a second switching circuit for sourcing additional current to the output terminal of the voltage regulator.  
   
     
     
         58 . A computer system, comprising: 
 a processor having a processor bus;    an input device coupled to the processor through the processor bus;    an output device coupled to the processor through the processor bus;    a memory device coupled to the processor bus, the memory device comprising: 
 a plurality of memory cells arranged in an array of rows and columns;  
 a plurality of devices for identifying cells within said array;  
 a plurality of pads;  
 a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;  
 a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof;  
 a transistor connected between a voltage source and the output terminal of said voltage regulator; and  
 a circuit for producing a control pulse of extended duration for input to said transistor, said circuit comprising: 
 a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration;  
 a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and  
 a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.  
 
   
     
     
         59 . A computer system, comprising: 
 a processor having a processor bus;    an input device coupled to the processor through the processor bus;    an output device coupled to the processor through the processor bus;    a memory device coupled to the processor bus, the memory device comprising: 
 a plurality of memory cells arranged in an array of rows and columns;  
 a plurality of devices for identifying cells within said array;  
 a plurality of pads;  
 a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;  
 a voltage bus;  
 a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof through said bus;  
 a plurality of switches for connecting each line of the voltage bus to a voltage source;  
 a switching circuit for sourcing additional current to an output terminal of said voltage regulator; and  
 a circuit for producing a control pulse of extended duration for input to said switching circuit, said circuit comprising: 
 a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration;  
 a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and  
 a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.  
 
   
     
     
         60 . A computer system, comprising: 
 a processor having a processor bus;    an input device coupled to the processor through the processor bus;    an output device coupled to the processor through the processor bus;    a memory device coupled to the processor bus, the memory device comprising: 
 a plurality of memory cells arranged in an array of rows and columns;  
 a plurality of devices for identifying cells within said array;  
 a plurality of pads;  
 a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;  
 a voltage bus;  
 a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof through said bus;  
 a plurality of switches for connecting each line of the voltage bus to a voltage source; 
 a first switching circuit including a p-channel device for sourcing additional current to an output terminal of said voltage regulator;  
 a second switching circuit including an n-channel transistor for sourcing additional current to an output terminal of said voltage regulator; and  
 a circuit for producing a control pulse of extended duration for input to said first and second switching circuits, said circuit comprising: 
 a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration;  
 a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and  
 a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.  
 
 
   
     
     
         61 . A computer system, comprising: 
 a processor having a processor bus;    an input device coupled to the processor through the processor bus;    an output device coupled to the processor through the processor bus;    a memory device coupled to the processor bus, the memory device comprising: 
 a plurality of memory cells arranged in an array of rows and columns;  
 a plurality of devices for identifying cells within said array;  
 a plurality of pads;  
 a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads;  
 a voltage regulator; a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks,  
 said voltage regulator comprising: 
 first and second output transistors;  
 an amplifier producing first and second output signals for controlling said first and second transistors, respectively;  
 a resistive and capacitive load connected across said first output transistor;  
 a circuit for providing a bias voltage to said amplifier in response to a control signal;  
 a first switch for connecting said control signal to ground; and  
 a second switch connected between said load and a predetermined voltage other than ground.  
 
   
     
     
         62 . A computer system, comprising: 
 a processor having a processor bus;    an input device coupled to the processor through the processor bus;    an output device coupled to the processor through the processor bus;    a memory device coupled to the processor bus, the memory device comprising: 
 a plurality of memory cells arranged in an array of rows and columns;  
 a plurality of devices for identifying cells within said array;  
 a plurality of pads; 
 a data path connecting said plurality of pads and said array, said data path including: 
 an output driver responsive to a data signal; and  
 a pre-driver providing variable output drive capability, comprising:  
  a plurality of output transistors; and  
  a plurality of switches for controlling the conductivity of said plurality of output transistors in response to signals indicative of the strength of output transistors in said output driver, said pre-driver for providing said data signal to said output driver.