Interface apparatus for integrated circuit testing
Abstract
An apparatus and method for coupling a test head and probe card in an IC testing system incorporating patterned divider elements disposed between rows of signal conductors to provide matching characteristic impedance values along each row of signal conductors. The divider elements have a conductive layer formed thereon that is electrically connected to ground. Openings of various shapes and sized are formed in the conductive layer to adjust the characteristic impedance of a corresponding signal conductor. A method for determining the patterning required for characteristic impedance matching is also provided. Test dividers are provided with openings of different size, and characteristic impedance measurements are taken with the various openings aligned to a signal conductor. The size opening is then interpolated to provide a particular characteristic impedance value. By sizing the openings corresponding to each signal conductor for the same characteristic impedance value, characteristic impedance matching is provided.
Claims
exact text as granted — not AI-modifiedWhat is claimed:
1 . An interface apparatus for integrated circuit testing, the apparatus comprising:
a first plate having first locations; a second plate having second locations; conductors extending between said first locations on said first plate and said second locations on said second plate; and a conductive divider element spanning across ones of said conductors, and comprising a pattern of conductive material.
2 . An apparatus according to claim 1 , wherein said pattern of conductive material includes non-conductive portions situated between conductive portions of said pattern.
3 . An apparatus according to claim 2 , wherein said conductive portions comprise a metal layer and said non-conductive portions comprise openings in said metal layer.
4 . An interface apparatus for integrated circuit testing according to claim 1 , wherein said pattern is selected to a provide a predetermined characteristic impedance to at least one of said conductors.
5 . An interface apparatus for integrated circuit testing according to claim 4 , wherein said characteristic impedance varies depending upon distance between said pattern and said conductors.
6 . An interface apparatus, comprising:
a plurality of plates; a plurality of conductors arranged in rows and extending between said plates; and a divider element situated between two rows of conductors, said divider element including a conductive sheeting with a non-conductive area situated therein.
7 . A method of providing an interface apparatus, said method comprising the steps of:
providing a plurality of plates; providing a plurality of conductors in rows and extending between said plates; identifying a location between two rows of said conductors at which a divider element is to be situated, and forming a conductive pattern on said divider element and locating it in said location to attempt to provide an expected affect on the characteristic impedance of ones of said conductors.
8 . A method of providing an interface apparatus according to claim 7 , said method further comprising the steps of:
measuring how said divider element affects characteristic impedance of said ones of said conductors; and modifying said conductive pattern so that an actual affect on characteristic impedance of ones of said conductors is closer to said expected affect.
9 . A method of providing an interface apparatus according to claim 7 , wherein said conductive pattern is formed based upon spatial relationships between and dimensions of said ones of said conductors and said conductive pattern.
10 . An interface apparatus, comprising:
a plurality of plates; a plurality of conductors arranged in rows and extending between said plates; wherein first ones of said conductors have a first cross-sectional area and second ones of said conductors have a second cross-sectional area to provide a desired characteristic impedance in at least one of said first ones of said conductors and said second ones of said conductors.
11 . An interface apparatus of claim 10 , wherein said desired characteristic impedance of said first ones of said conductors and said second ones of said conductors are substantially equal.
12 . An interface apparatus, comprising:
a plurality of plates; a plurality of signal conductors and ground conductors alternately arranged in rows and extending between said plates; wherein first ones of said ground conductors have a first cross-sectional area and second ones of said ground conductors have a second cross-sectional area to provide a desired characteristic impedance in at least one of said signal conductors adjacent said first ones of said conductors and said second ones of said conductors.
13 . An interface apparatus of claim 12 , wherein said desired characteristic impedance of said signal conductors adjacent said first ones of said conductors and said second ones of said conductors is substantially equal.
14 . An interface apparatus, comprising:
a plurality of plates; a plurality of signal conductors and ground conductors arranged in rows and extending between said plates; wherein the spacing between said signal conductors and said ground conductors is varied to provide desired characteristic impedances in said signal conductors.
15 . An interface apparatus according to claim 14 , wherein said characteristic impedances in said signal conductors are substantially equal.
16 . A divider element for affecting the characteristic impedance in one or more conductors in an adjacent row of conductors within an interface apparatus for integrated circuit testing, the divider element comprising a pattern of conductive material with non-conductive areas situated therein.Join the waitlist — get patent alerts
Track US2003011390A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.