Semiconductor test system and associated methods for wafer level acceptance testing

Abstract

A semiconductor test system includes at least one semiconductor wafer having working dies and at least one test die formed therein. Each of the working dies includes at least one bipolar transistor. A tester selectively supplies a changing direct current (DC) input signal to a selected test die and monitors a DC output signal therefrom. Each test die includes a test oscillator having at least one sample bipolar transistor substantially identical to the bipolar transistors of the working dies. The test oscillator switches between a non-oscillating state and an oscillating state as the DC input signal changes, and generates the DC output signal to the tester indicative of switching between the non-oscillating state and the oscillating state. A threshold level of a bias current that causes the test oscillator to switch between the non-oscillating state and the oscillating state is correlated to the maximum oscillation frequency and the transition frequency of the sample bipolar transistor.

That which is claimed is:  
     
         1 . A semiconductor test system comprising: 
 at least one semiconductor wafer comprising a plurality of working dies and at least one test die formed therein, each of said working dies comprising at least one bipolar transistor; and    a tester for selectively supplying a changing direct current (DC) input signal to said at least one test die and monitoring a DC output signal therefrom;    said at least one test die comprising a test oscillator including at least one sample bipolar transistor substantially identical to the bipolar transistors of said working dies;    said test oscillator switching between a non-oscillating state and an oscillating state as the DC input signal changes, and generating the DC output signal to said tester indicative of switching between the non-oscillating state and the oscillating state.    
     
     
         2 . A semiconductor test system according to  claim 1 , wherein the changing DC input signal comprises an increasing DC input signal.  
     
     
         3 . A semiconductor test system according to  claim 1 , wherein said at least one test die further comprises a bias current generator for generating a changing bias current to said at least one sample bipolar transistor based upon the changing DC input signal.  
     
     
         4 . A semiconductor test system according to  claim 3 , wherein said test oscillator switches between the non-oscillating and oscillating states based upon a threshold bias current which correlates with at least one high frequency parameter of said at least one sample bipolar transistor.  
     
     
         5 . A semiconductor test system according to  claim 4 , wherein the at least one high frequency parameter of said at least one sample bipolar transistor corresponds to at least one of a maximum oscillation frequency and a transition frequency.  
     
     
         6 . A semiconductor test system according to  claim 3 , wherein said at least one test die further comprises a dummy circuit connected to said test oscillator for maintaining a capacitance of said at least one sample bipolar transistor constant as the bias current changes.  
     
     
         7 . A semiconductor test system according to  claim 6 , wherein said dummy circuit comprises: 
 at least one second bipolar transistor substantially identical to said at least one sample bipolar transistor;    a coupling capacitor connecting said at least one second bipolar transistor to said at least one sample bipolar transistor; and    a second bias current generator for generating a second changing bias current to said at least one second bipolar transistor based upon the changing bias current generated for said at least one sample bipolar transistor.    
     
     
         8 . A semiconductor test system according to  claim 7 , wherein said at least one sample bipolar transistor has a first base-emitter capacitance and said at least one second bipolar transistor has a second base-emitter capacitance; and wherein the second changing bias current decreases as the bias current for said at least one sample bipolar transistor increases so that a combined base-emitter capacitance of said at least one sample and second bipolar transistors is relatively constant.  
     
     
         9 . A semiconductor test system according to  claim 1 , wherein said at least one test die further comprises a detector circuit connected to an output of said test oscillator for generating the DC output signal to said tester.  
     
     
         10 . A semiconductor test system according to  claim 9 , wherein said detector circuit comprises: 
 at least one output bipolar transistor comprising a base, a collector and an emitter;    a coupling capacitor connecting the base of said at least one output bipolar transistor to said at least one sample bipolar transistor;    at least one first diode-configured bipolar transistor connected between the base and the emitter of said at least one output bipolar transistor; and    at least one second diode-configured bipolar transistor connected between the base and the collector of said at least one output bipolar transistor.    
     
     
         11 . A semiconductor test system according to  claim 1 , wherein said test oscillator comprises a Colpitts oscillator.  
     
     
         12 . A semiconductor wafer comprising: 
 a semiconductor substrate;    a plurality of working dies on said semiconductor substrate, each of said working dies comprising at least one bipolar transistor; and    at least one test die on said semiconductor substrate, and comprising a test oscillator including at least one sample bipolar transistor substantially identical to the bipolar transistors of said working dies;    said test oscillator switching between a non-oscillating state and an oscillating state as a DC input signal being applied thereto changes, and generating a DC output signal indicative of switching between the non-oscillating state and the oscillating state.    
     
     
         13 . A semiconductor wafer according to  claim 12 , wherein the changing DC input signal comprises an increasing DC input signal.  
     
     
         14 . A semiconductor wafer according to  claim 12 , wherein said at least one test die further comprises a bias current generator for generating a changing bias current to said at least one sample bipolar transistor based upon the changing DC input signal.  
     
     
         15 . A semiconductor wafer according to  claim 14 , wherein said test oscillator switches between the non-oscillating and oscillating states based upon a threshold bias current which correlates with at least one high frequency parameter of said at least one sample bipolar transistor.  
     
     
         16 . A semiconductor wafer according to  claim 15 , wherein the at least one high frequency parameter of said at least one sample bipolar transistor corresponds to at least one of a maximum oscillation frequency and a transition frequency.  
     
     
         17 . A semiconductor wafer according to  claim 14 , wherein said at least one test die further comprises a dummy circuit connected to said test oscillator for maintaining a capacitance of said at least one sample bipolar transistor constant as the bias current changes.  
     
     
         18 . A semiconductor wafer according to  claim 17 , wherein said dummy circuit comprises: 
 at least one second bipolar transistor substantially identical to said at least one sample bipolar transistor;    a coupling capacitor connecting said at least one second bipolar transistor to said at least one sample bipolar transistor; and    a second bias current generator for generating a second changing bias current to said at least one second bipolar transistor based upon the changing bias current generated for said at least one sample bipolar transistor.    
     
     
         19 . A semiconductor wafer according to  claim 18 , wherein said at least one sample bipolar transistor has a first base-emitter capacitance and said at least one second bipolar transistor has a second base-emitter capacitance; and wherein the second changing bias current decreases as the bias current for said at least one sample bipolar transistor increases so that a combined base-emitter capacitance of said at least one sample and second bipolar transistors is relatively constant.  
     
     
         20 . A semiconductor wafer according to  claim 12 , wherein said at least one test die further comprises a detector circuit connected to an output of said test oscillator for generating the DC output signal.  
     
     
         21 . A semiconductor wafer according to  claim 20 , wherein said detector circuit comprises: 
 at least one output bipolar transistor comprising a base, a collector and an emitter;    a coupling capacitor connecting the base of said at least one output bipolar transistor to said at least one sample bipolar transistor;    at least one first diode-configured bipolar transistor connected between the base and the emitter of said at least one output bipolar transistor; and    at least one second diode-configured bipolar transistor connected between the base and the collector of said at least one output bipolar transistor.    
     
     
         22 . A semiconductor wafer according to  claim 12 , wherein said test oscillator comprises a Colpitts oscillator.  
     
     
         23 . A method for testing a semiconductor wafer comprising a plurality of working dies and at least one test die formed therein, each of the working dies comprising at least one bipolar transistor; the at least one test die comprising a test oscillator including at least one sample bipolar transistor substantially identical to the bipolar transistors of the working dies, the method comprising: 
 supplying a changing direct current (DC) input signal to the at least one test die so that the test oscillator switches between a non-oscillating state and an oscillating state;    generating a DC output signal indicative of switching between the non-oscillating state and the oscillating state; and    monitoring the DC output signal from the at least one test die.    
     
     
         24 . A method according to  claim 23 , wherein the supplying and monitoring is performed using a tester connected to the at least one test die.  
     
     
         25 . A method according to  claim 23 , wherein a level of the DC input signal increases as the DC input signal changes.  
     
     
         26 . A method according to  claim 23 , wherein the at least one test die further comprises a bias current generator for generating a changing bias current to the at least one sample bipolar transistor based upon the changing DC input signal.  
     
     
         27 . A method according to  claim 26 , wherein the test oscillator switches between the non-oscillating and oscillating states based upon a threshold bias current which correlates with at least one high frequency parameter of the at least one sample bipolar transistor.  
     
     
         28 . A method according to  claim 27 , wherein the at least one high frequency parameter of the at least one sample bipolar transistor corresponds to at least one of a maximum oscillation frequency and a transition frequency.  
     
     
         29 . A method according to  claim 26 , wherein the at least one test die further comprises a dummy circuit connected to the test oscillator for maintaining a capacitance of the at least one sample bipolar transistor constant as the bias current changes.  
     
     
         30 . A method according to  claim 29 , wherein the dummy circuit comprises at least one second bipolar transistor substantially identical to the at least one sample bipolar transistor; and a coupling capacitor connecting the at least one second bipolar transistor to the at least one sample bipolar transistor; and further comprising: 
 generating a second changing bias current using a second bias current generator, for the at least one second bipolar transistor based upon the changing bias current generated for the at least one sample bipolar transistor.    
     
     
         31 . A method according to claim  30 , wherein the at least one sample bipolar transistor has a first base-emitter capacitance and the at least one second bipolar transistor has a second base-emitter capacitance; and wherein the second changing bias current decreases as the bias current for the at least one sample bipolar transistor increases so that a combined base-emitter capacitance of the at least one sample and second bipolar transistors is relatively constant.  
     
     
         32 . A method according to  claim 23 , wherein the at least one test die further comprises a detector circuit connected to an output of the test oscillator for generating the DC output signal.