Signal processing device accessible as memory

Abstract

A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

What is claimed is:  
     
         1 . A computer program product for data processing using a plurality of information processing units which are connected in series via communication links and incorporated in a computer having a CPU and a bus, each of said information processing units being accessible as a memory by said CPU via said bus, said computer program product comprising: 
 a computer usable medium providing program-code means for controlling said computer so as to cause said information processing units to carry out said data processing, said program-code means comprising:    first resource-management means for controlling process allocation to said information processing units and data connection between said information processing units in response to a request for said data processing from an application program; and    second resource-management means for controlling said information processing units to carry out said data processing according to said process allocation and said data connection,    wherein said first resource-management means resides in an application interface layer of software of said computer, and said second resource-management means resides in a device-driver layer of said software of-said computer.    
     
     
         2 . The computer program product as claimed in  claim 14 , wherein said first resource-management means establishes parallel data connections between said information processing units such that said information processing units carry out parallel processing.  
     
     
         3 . The computer program product as claimed in  claim 14 , wherein said first resource-management means establishes serial data connections between said information processing units such that said information processing units carry out a pipe-line operation by successively passing data from a given one of said information processing units to a next one of said information processing units.  
     
     
         4 . The computer program product as claimed in  claim 14 , wherein said computer-code means further comprises virtual-machine means for detecting an interruption when said interruption is generated by said CPU executing said application program and for. handing an instruction causing said interruption in said application program to said first resource-management means, wherein said first resource-management means and said second resource-management means control said information processing units to execute said instruction.  
     
     
         5 . The computer program product as claimed in  claim 14 , wherein said first resource-management means controls said process allocation so as to minimize a maximum amount of data transfer between said information processing units after said process allocation.  
     
     
         6 . The computer program product as claimed in  claim 14 , wherein said first resource-management means comprises: 
 first process-allocation means for obtaining combinations of said information processing units for said process allocation such that a maximum amount of data transfer between said information processing units after said process allocation is minimized; and    second process-allocation means for selecting one of said combinations such that said information processing units remaining unallocated after said process allocation are provided in a range defined by as small a number of said communication links as possible.    
     
     
         7 . A software architecture comprising: 
 an application layer in which application programs are provided;    an application interface layer in which dynamic loading libraries are provided to be dynamically loaded when said application programs are executed;    a device-driver layer in which device drivers are provided to control hardware devices corresponding to respective ones of said dynamic loading libraries; and    a resource-management program provided in said application interface layer and said device-driver layer, said resource-management program controlling a plurality of information processing elements implemented as a hardware device and controlling process allocation to said information processing elements and data connection between said information processing elements.    
     
     
         8 . A method of allocating a process to a plurality of information processing units connected in series via communication links so as to communicate with each other, said method comprising: 
 obtaining combinations of said information processing units for process allocation such that a maximum amount of data transfer between said information processing units after said process allocation is minimized; and    selecting one of said combinations such that said information processing units remaining unallocated after said process allocation are provided in a range defined by as small a number of said communication links as possible.    
     
     
         9 . A method of controlling at least one client processor connected to a host processor having a main memory, said method comprising the steps of: 
 a) accessing a memory space of said main memory from said host processor; and    b) allocating a portion of said memory space for use for communication between said host processor and said at least one client processor in response to said accessing.    
     
     
         10 . The method as claimed in  claim 22 , further comprising a step of disconnecting said at least one client processor from said host processor by releasing said portion of said memory space in response to said accessing.  
     
     
         11 . The method as claimed in  claim 22 , wherein said accessing comprises a plurality of accesses which are made to a predetermined address.  
     
     
         12 . The method as claimed in  claim 22 , wherein said accessing comprises a plurality of accesses which are made within a predetermined range of addresses.  
     
     
         13 . The method as claimed in  claim 22 , wherein said step a) comprises a step of writing data including a key in said memory space, and said step b) comprises a step of allocating said portion of said memory space for said use for said communication when said key matches a predetermined key.  
     
     
         14 . The method as claimed in  claim 26 , wherein said step a) comprises a step of writing a data word including a plurality of identical sub-words in said memory space, each of said sub-words being said key.  
     
     
         15 . The method as claimed in  claim 26 , wherein said step a) comprises a step of writing data words in said memory space, said data words including data words comprised of only is and data words comprised of only 0s, said key being represented as a time series of is and Os each of which is taken from a corresponding one of said. data words.  
     
     
         16 . The method as claimed in  claim 26 , wherein said step a) comprises a step of writing data words in said memory space, said key being represented by one of a number of 1s and a number of Os included in each of said data words.  
     
     
         17 . The method as claimed in  claim 26 , wherein said step b) further comprises a step of counting a number of accesses of said accessing, and allocates said portion of, said memory space for said use for said communication when said number is a predetermined number.  
     
     
         18 . The method as claimed in  claim 26 , wherein said step b) further comprises a step of checking parity of said data and deciding that said key fails to match said predetermined key without actually checking said key when said parity fails to meet a predetermined parity condition.  
     
     
         19 . The method as claimed in  claim 26 , wherein said step b) further comprises a step of checking a predetermined set of bits included in said data and deciding that said key fails to match said predetermined key without actually checking said key when said predetermined set of bits fails to match a predetermined bit pattern.  
     
     
         20 . The method as claimed in  claim 28 , wherein said step b) further comprises a step of deciding that said key fails to match said predetermined key without actually checking said key when one of said data words is comprised of bits of. different values.  
     
     
         21 . The method as claimed in  claim 22 , wherein said step b) further comprises a step of allocating said at least one client processor to said portion of said memory space after moving an application to another portion of said memory space when said portion of said memory space is occupied by said application.  
     
     
         22 . The method as claimed in  claim 22 , further comprising a step of controlling allocation of said portion of said memory space for said at least one client processor and allocation of an application to said at least one client processor independently from each other.  
     
     
         23 . The method as claimed in  claim 22 , further comprising a step of establishing synchronization between said host processor and said at least one client processor, and a step of establishing synchronization between a plurality of client processors inclusive of said at least one client processor.  
     
     
         24 . A machine readable medium having a program embodied therein for controlling at least one client processor connected to a host processor having a main memory, said program comprising: 
 first program code means for accessing a memory space of said main memory from said host processor; and    second program code means for allocating a portion of said memory space for use for communication between said host processor and said at least one client processor in response to said accessing.    
     
     
         25 . The machine readable medium as claimed in claim  37 , further comprising a program code means for disconnecting said at least one client processor from said host processor by releasing said portion of said memory space in response to said-accessing.  
     
     
         26 . The machine readable medium as claimed in claim  37 , wherein said second program code means further comprises program code means for allocating said at least one client processor to said portion of said memory space after moving an application to another portion of said memory space when said portion of said memory space is occupied by said application.  
     
     
         27 . The machine readable medium as claimed in claim  37 , further comprising program code means for controlling allocation of said portion of said memory space for said at least one client processor and allocation of an application to said at least one client processor independently from each other.  
     
     
         28 . The machine readable medium as claimed in claim  37 , further comprising program code means for establishing synchronization between said host processor and said at least one client processor, and a step of establishing synchronization between a plurality of client processors inclusive of said at least one client processor.  
     
     
         29 . A device for signal processing connected to a host processor through an external bus and comprising: 
 information processing units comprising respective DRAMs coupled to the external bus, said information processing units connected to each other by a communication link and to each other and to the host processor by the external bus through the respective DRAMs, and said information processing units exchanging data with each other through the communication link and the respective DRAMs and processing data while exchanging data with the host processor through only the respective DRAMs.