Dram module and method of using sram to replace damaged dram cell

Abstract

A DRAM module and a method of replacing a damaged DRAM cell in the DRAM module with a SRAM. The DRAM module has at least a non-volatile memory and a DRAM control logic circuit. In the process of replacing the damaged DRAM with the SRAM, the damaged address data is compared to DRAM address data. If the data are consistent, the address of the SRAM is used to access data. Meanwhile, the output enabling signal of the DRAM cell is turned off. It can thus assist the computer to correctly find the good DRAM cell for data access, so as to ensure a normal operation of the computer.

What is claimed is:  
     
         1 . A DRAM module using a SRAM to replace a damaged DRAM cell, the DRAM module coupled to a system bus and being activated by a power up signal, comprising: 
 an address recorder, to pre-store a plurality of damaged address data, and to output the damaged address data by a power up signal;    a means for identifying and comparing a plurality of address, coupled to the address recorder, to write the damaged address data therein, and to receive a DRAM address data to compare to the damaged address data to output a match signal, wherein the comparison of address data is implemented by comparing the content of the address data;    a SRAM, coupled to the means for identifying and comparing a plurality of address to receive the match signal, and to access a data signal according to the match signal and a DRAM control signal;    a DRAM, coupled to the means for identifying and comparing a plurality of address to receive the match signal and the DRAM address data, and to access the data signal according to the match signal, the DRAM address signal and the DRAM control signal; and    a DRAM control logic circuit, coupled to the system bus, the means for identifying and comparing a plurality of address, the DRAM control signal and the data signal, to perform one of the following operations: 
 data signal access in the SRAM;  
 data signal access in the DRAM; and  
 data written into the means for identifying and comparing a plurality of address.  
   
     
     
         2 . The DRAM module according to  claim 1 , wherein the address recorder comprises a flash memory.  
     
     
         3 . The DRAM module according to  claim 1 , wherein the address recorder comprises an electrically erasable programmable read only memory.  
     
     
         4 . The DRAM module according to  claim 1 , wherein the address recorder comprises an electrically programmable read only memory.  
     
     
         5 . The DRAM module according to  claim 1 , wherein the address recorder comprises a programmable logic array.  
     
     
         6 . The DRAM module according to  claim 1 , wherein the address recorder comprises a programmable fuse.  
     
     
         7 . The DRAM module according to  claim 1 , wherein the damaged address data are written in the means for identifying and comparing a plurality of address by a software.  
     
     
         8 . The DRAM module according to  claim 1 , wherein when the DRAM address data is the same as one of the damaged address data, the match signal is activated to enable a certain address of the SRAM, and to disable an output enabling signal of the DRAM.  
     
     
         9 . The DRAM module according to  claim 1 , wherein when the DRAM address data is not the same as any of the damaged address data, the match signal is disabled, so that the DRAM is operated normally without enabling the SRAM.  
     
     
         10 . The DRAM module according to  claim 1 , wherein the damaged address data provides a parity bit to determine whether the damaged address data are either valid or invalid data.  
     
     
         11 . The DRAM module according to  claim 10 , wherein when the damaged address data are invalid data, the parity bit disables the match signal.  
     
     
         12 . An apparatus using a SRAM to replace a damaged DRAM cell, coupled to a SRAM, a DRAM and a system bus, the apparatus comprising: 
 an address recorder, to pre-store a plurality of damaged address data;    a means for identifying and comparing a plurality of address, coupled to the address recorder, the SRAM and the DRAM, to compare the damaged address data with a DRAM address data to output a match signal, wherein the comparison of the damaged address is implemented by comparing the content of the address data; and    a DRAM control logic circuit, coupled to the system bus, the a means for identifying and comparing a plurality of address, the DRAM and the SRAM, to receive the DRAM address data a DRAM control signal and a data signal.    
     
     
         13 . The apparatus according to  claim 12 , wherein, the DRAM control logic circuit at least perform one of the following operations: 
 data signal processing in the SRAM;    data signal processing in the DRAM; and    writing the data signal in the content addressable memory.    
     
     
         14 . A method of using a SRAM to replace a damaged DRAM cell, comprising 
 pre-storing a plurality of damaged address data into an address recorder; and    coupling the address recorder with a means for identifying and comparing a plurality of address, the SRAM and the DRAM, wherein the damaged address data is compared with a DRAM address data comparing their content to output a match signal.    
     
     
         15 . The apparatus according to  claim 14 , wherein the damaged address data comprises a flash memory.  
     
     
         16 . The apparatus according to  claim 14 , wherein damaged address data comprises an electrically erasable programmable read only memory.  
     
     
         17 . The apparatus according to  claim 14 , wherein the damaged address data comprises an electrically programmable read only memory.  
     
     
         18 . The apparatus according to  claim 14 , wherein the damaged address data comprises a programmable logic array.  
     
     
         19 . The apparatus according to  claim 14 , wherein the damaged address data comprises a programmable fuse.  
     
     
         20 . The apparatus according to  claim 14 , wherein the damaged address data are written into the means for identifying and comparing a plurality of address by a software.  
     
     
         21 . The apparatus according to  claim 14 , wherein when the DRAM address data is the same as one of the damaged address data, the match signal is activated to enable a certain address of the SRAM, and an output enabling signal of the DRAM is disabled.  
     
     
         22 . The apparatus according to  claim 14 , wherein when the DRAM address signal is different from any of the damaged address data, the match signal is disabled, the SRAM is not enabled, and the DRAM is operated normally.  
     
     
         23 . The apparatus according to  claim 14 , wherein the damaged address data provide a parity bit to determine whether the damaged address data are valid or invalid data.  
     
     
         24 . The apparatus according to  claim 14 , wherein the parity bit disable the match signal when the damaged address data are invalid.