US2002196352A1PendingUtilityA1

Compensation of pixel source follower variations in CMOS imager

Priority: May 21, 2001Filed: May 21, 2002Published: Dec 26, 2002
Est. expiryMay 21, 2021(expired)· nominal 20-yr term from priority
H04N 25/75H04N 25/67H10F 39/18
44
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Claims

Abstract

An arrayed source-follower buffer arrangement compensates between gains of respective columns of a pixel array. For each said column of the pixel array the source-follower buffer arrangement includes an operational amplifier having a signal input, an output, and a feedback terminal and a source-follower amplifier disposed with a gate coupled to the output, a terminal connected to a bias voltage, and an output terminal connected to the feedback terminal of the operational amplifier. The bias voltage may be matched to a bias voltage applied to the pixel array. A source-follower construction compensates for body effect and load effect by having a reference source follower per column of the same dimensions used as in the pixel array.

Claims

exact text as granted — not AI-modified
I claim:  
     
         1 . An arrayed source-follower buffer arrangement for compensating between gains of respective columns of a pixel array; wherein for each said column of the pixel array the source-follower buffer arrangement includes 
 a) an operational amplifier having a signal input, an output, and a feedback terminal; and    b) a source-follower amplifier disposed with a gate coupled to said output, a terminal connected to a bias voltage, and an output terminal connected to the feedback terminal of the operational amplifier.    
     
     
         2 . The buffer arrangement of  claim 1  wherein said bias voltage is matched to a bias voltage applied to the pixel array.  
     
     
         3 . The buffer arrangement of  claim 1 , wherein said operational amplifier has matching loads applied to each of a pair of (+) and (−) inputs thereof.  
     
     
         4 . The buffer arrangement of  claim 3 , wherein said loads are each formed of a source follower.  
     
     
         5 . The buffer arrangement of  claim 4 , wherein an adjustable bias is applied to gate terminals of said source followers to control the load values thereof.

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