Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells

Abstract

There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zone of the active area in which the cell plate electrode is not formed and serves as a gate electrode of the field effect transistor on the active area, the word line pattern being formed through a gate oxide at a predetermined interval, wherein the layout of a cell array of the memory cells is provided by a closest packing cell configuration.

What is claimed is:  
     
         1 . A semiconductor integrated circuit device comprising: 
 a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, said field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size;    a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to said active area and a cell plate electrode formed so as to cover part of said active area with a predetermined cell plate pattern through a capacitor dielectric, said cell plate pattern extending in said transverse direction with a certain length size; and    a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zone of said active area in which said cell plate electrode is not formed and serves as a gate electrode of said field effect transistor on said active area, said word line pattern being formed through a gate oxide at a predetermined interval,    wherein the layout of a cell array of said memory cells is provided by a closest packing cell configuration.    
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , wherein the pitch of the memory cell in the transverse direction is loosened and at least two bit lines are arranged for each pitch of the memory cell in the longitudinal direction.  
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 , wherein the thickness of the capacitor dielectric is the same as that of the gate oxide.  
     
     
         4 . The semiconductor integrated circuit device according to  claim 1 , wherein the capacitor dielectric is made thinner than the gate oxide.  
     
     
         5 . The semiconductor integrated circuit device according to  claim 1 , wherein another first conductance-type diffusion having a highly doped diffusion region is provided under said diffusion region.  
     
     
         6 . The semiconductor integrated circuit device according to  claim 1 , wherein the capacitor structure has a trench structure.  
     
     
         7 . The semiconductor integrated circuit device according to  claim 1 , wherein the first conductance-type is p-type and the second conductance-type is n-type, or the first conductance-type is n-type and the second conductance-type is p-type.  
     
     
         8 . A method of manufacturing a semiconductor integrated circuit device comprising: 
 a first step of forming an active area and a device isolation region on the main surface of a semiconductor substrate and creating a field pattern of a memory cell array having a plurality of memory cells;    a second step of carrying out an impurity implant on said main surface to form a first conductance type well region which extends to a certain depth;    a third step of creating a resist pattern which covers part of said active area to form a second conductance-type diffusion region by carrying out the impurity implant through said resist pattern;    a fourth step of forming in turn a insulating film and an wiring layer each having a predetermined thickness after removing said resist pattern;    a fifth step of etching said wiring layer through a desired pattern created on the top for a microfabrication to form a gate electrode of a field effect transistor and a cell plate electrode;    a sixth step of forming insulating sidewalls to said gate electrode and said cell plate to form a highly doped diffusion region with the second conductance-type through a high-dose ion implant;    a seventh step of forming a first interlayer dielectric to open a contact hole therein by a microfabrication; and    an eighth step of forming a metal wiring layer and creating a metal wiring from said wiring layer through a microfabrication.    
     
     
         9 . The method of manufacturing a semiconductor integrated circuit device according to  claim 8 , wherein the third step includes a step of forming a highly doped diffusion region with the first conductance-type extending under said second conductance-type diffusion region.  
     
     
         10 . The method of manufacturing a semiconductor integrated circuit device according to  claim 8 , wherein the second step includes a step of forming another insulating film after formation of said well region and the third step includes a step of removing said another insulating film after formation of said second conductance-type diffusion region  
     
     
         11 . The method of manufacturing a semiconductor integrated circuit device according to  claim 8 , wherein the first step includes a step of forming a trench within a section of the memory cell array.  
     
     
         12 . The method of manufacturing a semiconductor integrated circuit device according to  claim 8 , wherein the first conductance-type is p-type and the second conductance-type is n-type, or the first conductance-type is n-type and the second conductance-type is p-type.  
     
     
         13 . A memory size calculation method of DRAM memory cells characterized in that a cell size of a planar-type capacitor in a memory cell laid out in accordance with a closest packing cell configuration is found based on a minimum microfabrication dimension.  
     
     
         14 . A memory size calculation method for DRAM memory cells that when the cell sizes in the transverse and longitudinal directions are represented nxF and nyF, respectively, based on a minimum microfabrication dimension F, and a capacitor area for a signal and a cell area are represented Scap and Scell, respectively, respectively, and under the conditions of na≧2.5, nx≧2 (integer), and ny≧2 (integer), the na, nx, and ny values are derived so as to bring the cell area Scell to a minimum based on the following formulae (1) and (2):  
         Scap =( nxF−F )·( nyF−naF− 0.5 F )  (1)  
         Scell=nxF·nyF   (2)