Semiconductor device and manufacturing method of the same

Abstract

A gate electrode rectangular in section is formed by patterning on a GaAs substrate as a compound substrate having a channel layer. Subsequently, a specific metal, e.g., Ti is deposited. A solid-phase reaction layer to serve as source/drain is formed in a self-alignment manner with the gate electrode by a thermal treatment. The part of the Ti film which has not been reacted is then removed. Thus the source/drain (or at least one of them) are very easily formed to a shallow junction depth without using any ion implantation process. Realized is a semiconductor device showing an excellent device characteristics, capable of suppressing occurrence of short-channel effect even in its shortened gate length for reducing the device size.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a substrate having a compound semiconductor;    a gate electrode formed on said substrate; and    source/drain regions formed in said substrate,    wherein at least one of said source/drain regions is a solid-phase reaction layer of said compound semiconductor and a specific metal, and    electrodes are electrically connected to said source/drain regions respectively.    
     
     
         2 . The device according to  claim 1 , wherein 
 said specific metal is one selected among Ti, Co, Ni, Pd and Mo.    
     
     
         3 . The device according to  claim 1 , wherein 
 said solid-phase reaction layer is so formed as to be shallow at a portion near said gate electrode and deep on the periphery of said portion.    
     
     
         4 . The device according to  claim 1 , wherein 
 said device has a MESFET or HEMT structure.    
     
     
         5 . The device according to  claim 1 , wherein 
 an insulating substance is so formed as to cover either side of said gate electrode.    
     
     
         6 . A manufacturing method of a semiconductor device which includes a substrate made of a compound semiconductor, a gate electrode formed on said substrate, and source/drain regions formed in said substrate, said method comprising the steps of: 
 forming said gate electrode on a channel layer of said substrate;    forming a film of a specific metal onto said substrate so as to cover at least one of side portions of said gate electrode;    reacting said compound semiconductor with said specific metal in solid phase to form at least one solid-phase reaction layer in said substrate; and    removing the part of said film which has not been reacted,    so that at least one of said source/drain regions is made of said solid-phase reaction layer.    
     
     
         7 . The method according to  claim 6 , wherein 
 said film is so formed as to cover the upper and side portions of said gate electrode, so that said solid-phase reaction layer is formed in a self-alignment manner with said gate electrode.    
     
     
         8 . The method according to  claim 6 , wherein 
 said part of said film which has not been reacted is removed by etching, and the gate length of said gate electrode is shortened in the etching process.    
     
     
         9 . The method according to  claim 6 , wherein 
 said film is so formed as to have its thickness at a portion near said gate electrode larger than its thickness on the periphery of said portion,    so that said solid-phase reaction layer is formed to be shallow at said portion and deep on said periphery.    
     
     
         10 . The method according to  claim 6 , wherein 
 either side of said gate electrode is covered with an insulating material, and said film is formed in this state.    
     
     
         11 . The method according to  claim 6 , wherein 
 said film is formed in the state that one side of said gate electrode is covered with a mask, and then said mask is removed, so that said solid-phase reaction layer is formed only on said one side of said gate electrode.    
     
     
         12 . The method according to  claim 6 , wherein 
 said device is manufactured into a MESFET or HEMT structure.    
     
     
         13 . The method according to  claim 6 , wherein 
 said specific metal is one selected among Ti, Co, Ni, Pd and Mo.