Simultaneous built-in self-testing of multiple identical blocks of integrated circuitry

Abstract

n identical integrated circuit blocks are simultaneously tested for defects. Each block contains m scan chains. The i th scan chains in each block are identical (i=1, 2, . . . , m). During an i th clock cycle, an i th test vector is simultaneously applied to each block's i th scan chain. The resultant n output signals are compared. If all n outputs are equal the i th scan chain is designated defect-free for all n blocks; otherwise, the i th scan chain is designated defective for one or more blocks. After sequentially repeating the test vector application, output comparison and designation process for i=1, 2, . . . , m the n blocks are designated defect-free if all m scan chains have been designated defect-free for all n blocks; otherwise, if one or more scan chains have been designated defective for one or more blocks, the n blocks are designated defective.

What is claimed is:  
     
         1 . A method of testing for defects in n identical blocks of circuitry on an integrated circuit device, each one of said blocks containing m logic gate scan chains, each i th  one of said scan chains in each one of said blocks being identical, where i=1, 2, . . . , m, said method comprising: 
 (a) during an i th  clock cycle, simultaneously applying an i th  test vector to said i th  ones of said scan chains in each one of said blocks;    (b) during said i th  clock cycle, simultaneously comparing n output signals produced by said i th  ones of said scan chains in each one of said blocks;    (c) if said comparison reveals that all of said n output signals are equal, designating said i th  ones of said scan chains defect-free for all of said n blocks;    (d) if said comparison reveals that all of said n output signals are not equal, designating said i th  ones of said scan chains defective for one or more of said n blocks;    (e) sequentially repeating said applying, said comparing and said designating for each value of i=1, 2, . . . , m;    (f) if all in of said scan chains are designated defect-free for all of said n blocks, designating said n identical blocks of circuitry defect-free; and,    (g) if one or more of said scan chains are designated defective for one or more of said n blocks, designating said n identical blocks of circuitry defective.    
     
     
         2 . A method as defined in  claim 1 , wherein said test vectors are random bit patterns.  
     
     
         3 . A method as defined in  claim 1 , further comprising, during said i th  clock cycle, generating said i th  test vector as a random bit pattern.  
     
     
         4 . A method as defined in  claim 1 , further comprising, during said i th  clock cycle, generating said i th  test vector as a pre-defined non-random bit pattern.  
     
     
         5 . A method as defined in  claim 4 , wherein said pre-defined non-random bit pattern further comprises an alternating pattern of logic “0's” and logic “1's”.  
     
     
         6 . A method as defined in  claim 1 , further comprising masking all but a selected one of said n output signals to thereby select for defect testing only that one of said blocks which produces said selected one of said n output signals.  
     
     
         7 . Apparatus for testing for defects in n identical blocks of circuitry on an integrated circuit device, each one of said blocks containing m logic gate scan chains, each i th  one of said scan chains in each one of said blocks being identical, where i=1, 2, . . . , m, said apparatus comprising: 
 (a) a test vector generator connected to an input of said each i th  one of said scan chains in each one of said blocks to simultaneously apply an i th  test vector to said each i th  one of said scan chains in each one of said blocks during an i th  clock cycle;    (b) a comparator connected to an output of said each i th  one of said scan chains in each one of said blocks to simultaneously compare n output signals produced by said i th  ones of said scan chains in each one of said blocks during said i th  clock cycle, said comparator producing: 
 (i) a pass output signal designating said i th  ones of said scan chains defect-free for all of said n blocks if all of said n output signals are equal; and,  
 (ii) a fail output signal designating said i th  ones of said scan chains defective for one or more of said n blocks if all of said n output signals are not equal.  
   
     
     
         8 . Apparatus as defined in  claim 7 , said test vector generator further comprising m test vector outputs, each i th  one of said test vector outputs connected to an input of said each i th  one of said scan chains in each one of said blocks.  
     
     
         9 . Apparatus as defined in  claim 7 , said comparator further comprising m n-input sub-comparators, each i th  one of said sub-comparators having a j th  input connected to an output of a one of said j th  scan chains in each one of said blocks, where j=1, 2, . . . , n.  
     
     
         10 . Apparatus as defined in  claim 9 , further comprising an m-input AND gate each i th  one of said AND gate inputs connected to an output of an i th  one of said sub-comparators.  
     
     
         11 . Apparatus as defined in  claim 7 , said test vector generator further comprising a linear feedback shift register.  
     
     
         12 . Apparatus as defined in  claim 11 , said linear feedback shift register further comprising m D-type flip-flops, m reconfigurable connection lines and m−1 reconfigurable exclusive-OR gates, each j th  one of said connection lines having an input connected to a Q output of a j th  one of said flip-flops, where j=1, 2, . . ., m, each k th  one of said exclusive-OR gates having a first input connected to an output of a k th  one of said connection lines and a second input connected to an output of a k+1 th  one of said exclusive-OR gates, where k=1, 2, . . . , m−2, an m−1 th  one of said exclusive-OR gates having a first input connected to an output of an m−1 th  one of said connection lines and a second input connected to an output of an m th  one of said connection lines.  
     
     
         13 . Apparatus as defined in  claim 12 , said linear feedback shift register further comprising m 2-input multiplexors, each j th  one of said 2-input multiplexors excepting a j=1 one of said 2-input multiplexors having: 
 (a) an output connected to a D input of a j th  one of said flip-flops;    (b) a first input connected to a {overscore (Q)} output of said j th  one of said flip-flops;    (c) a second input connected to a Q output of a j−1 th  one of said flip-flops;    said j=1 one of said 2-input multiplexors having:    (d) an output connected to a D input of said j=1 one of said 2-input multiplexors;    (e) a first input connected to a {overscore (Q)} output of said j=1 one of said 2-input multiplexors; and,    (f) a second input connected to an output of a k=1 one of said exclusive-OR gates;    each one of said 2-input multiplexors having an output selectably connectible to either one of said first or said second inputs of said one of said 2-input multiplexors.    
     
     
         14 . Apparatus as defined in  claim 9 , each one of said sub-comparators further comprising: 
 (a) an n-input NOR gate, each j th  one of said NOR gate inputs connected to an output of a j th  one of said i th  scan chains in each one of said blocks;    (b) an n-input AND gate, each j th  one of said AND gate inputs connected to an output of a j th  one of said i th  scan chains in each one of said blocks; and,    (c) a 2-input OR gate having a first input connected to an output of said NOR gate and a second output connected to an output of said AND gate.    
     
     
         15 . Apparatus as defined in  claim 14 , each one of said sub-comparators further comprising: 
 (a) first and second D-type flip-flops, said first flip-flop having a D input connected to an output of said OR gate, said second flip-flop having a D input connected to a Q output of said first flip-flop;    (b) a 2-input exclusive-OR gate having a first input connected to a Q output of said first flip-flop and a second input connected to a Q output of said second flip-flop; and,    (c) a 2-input multiplexor having a first input connected to said output of said OR gate, a second input connected to an output of said exclusive-OR gate and an output selectably connectible to either one of said first or said second inputs of said 2-input multiplexor.    
     
     
         16 . Apparatus as defined in  claim 7 , further comprising a controller for producing n block select signals, each j th  one of said block select signals coupled to a j th  one of said blocks, where j=1, 2, . . . , n, wherein all of said output signals produced by all of said scan chains in said j th  one of said blocks are masked if said j th  one of said block select signals has a first logic value and all of said output signals produced by all of said scan chains in said j th  one of said blocks are not masked if said j th  one of said block select signals has a second logic value opposite to said first logic value.  
     
     
         17 . Apparatus as defined in  claim 16 , said controller further comprising, for each i th  one of said scan chains in each j th  one of said blocks, an ij th  2-input AND gate having a first input connected to said output of said i th  one of said scan chains in said j th  one of said blocks, and having a second input connected to said j th  one of said block select signals.