Memory system for ordering load and store instructions in a processor that performs out-of-order multithread execution

Abstract

In one embodiment of the invention, a processor includes a memory order buffer (MOB) including load buffers and store buffers, wherein the MOB orders load and store instructions so as to maintain data coherency between load and store instructions in different threads, wherein at least one of the threads is dependent on at least another one of the threads. In another embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads, the execution pipeline including a memory order buffer that orders load and store instructions. The processor also includes detection circuitry to detect speculation errors associated with load instructions in a load buffer.

What is claimed is:  
     
         1 . A processor comprising: 
 a memory order buffer (MOB) including load buffers and store buffers, wherein the MOB orders load and store instructions so as to maintain data coherency between load and store instructions in different threads, wherein at least one of the threads is dependent on at least another one of the threads.    
     
     
         2 . The processor of  claim 1 , further comprising thread management logic to control dynamic creation of the threads.  
     
     
         3 . The processor of  claim 1 , further comprising thread management logic to provide an indication of program order and retirement order.  
     
     
         4 . The processor of  claim 3 , wherein threads are retired from the MOB in retirement order in a final retirement.  
     
     
         5 . The processor of  claim 3 , wherein threads are retired from the MOB in retirement order in a final retirement after it is assured that all instructions have been executed without speculation error or have been part of a reset thread.  
     
     
         6 . The processor of  claim 1 , wherein the store buffer includes a field to hold data to be store to memory.  
     
     
         7 . The processor of  claim 1 , wherein load buffer includes status fields including indication has to whether a load instruction had previously received data from memory or data in the store buffer.  
     
     
         8 . The processor of  claim 1 , wherein load buffer includes status fields including indication has to a store buffer identification number (SBID) of a store buffer entry from which the load instruction previously received data.  
     
     
         9 . The processor of  claim 1 , wherein load buffer includes status fields including indication has to a thread identification number of a store instruction from which the load instruction previously received data.  
     
     
         10 . A processor, comprising: 
 an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads, the execution pipeline including a memory order buffer that orders load and store instructions; and    detection circuitry to detect speculation errors associated with load instructions in a load buffer.    
     
     
         11 . The processor of  claim 10 , further including replay triggering circuitry.  
     
     
         12 . The processor of  claim 10 , further including a trace buffer outside the execution pipeline that holds the load and store instructions until a final retirement.  
     
     
         13 . The processor of  claim 10 , wherein the detection circuitry is included in the execution pipeline.  
     
     
         14 . A processor comprising: 
 a memory order buffer including: 
 load buffers to hold load instructions of threads;  
 store buffers to hold store instructions of the threads; and  
 comparison circuitry to compare an address of one of the load instructions to be executed with addresses of at least one of the store instructions in the store buffers;  
 date path control logic to determine whether the load instruction reads data from memory or from one of the store buffers.  
   
     
     
         15 . A processor comprising: 
 a memory order buffer including: 
 load buffers to hold load instructions of threads;  
 store buffers to hold store instructions of the threads; and  
 comparison circuitry to compare an address and status bits of one of the store instructions to be executed with addresses and status bits of at least one of the load instructions; and  
 detection logic to determine whether to replay one or more of the load instructions based on the comparison.