Multi-processor type storage control apparatus for performing access control through selector

Abstract

A storage control apparatus is coupled to a central processing unit (CPU) and a storage unit to control input/output of data between the CPU and the storage unit. The storage control apparatus has at least two processors coupled to the CPU and the storage unit, a cashe memory (CM) unit for temporarily storing data of the storage unit, a shared memory (SM) unit for storing information concerning control of the CM unit and the storage unit, and a selector coupled to the at least two processors, the CM unit and the SM unit through access paths to selectively apply access requests from the at least two processors to the CM unit and the SM unit.

1 . A storage control apparatus coupled to a central processing unit and a storage unit to control input/output of data between said central processing unit and said storage unit, comprising: 
 at least two processors coupled to said central processing unit and said storage unit;    a cashe memory unit for temporarily storing data of said storage unit;    a shared memory unit for storing information concerning control of said cashe memory unit and said storage unit; and    a selector coupled to each of said at least two processors, said cashe memory unit and said shared memory unit through access paths to selectively apply access requests from said at least two processors to said cashe memory unit and said shared memory unit.    
     
     
         2 . A storage control apparatus according to  claim 1 , wherein the total number of access paths for coupling said selector and said shared memory unit or the total number of access paths for coupling said selector and said cashe memory unit is smaller than the total number of access paths for coupling each of said at least two processors and said selector.  
     
     
         3 . A storage control apparatus according to  claim 1 , wherein said shared memory unit includes paired two shared memory sections each coupled to said selector, said two shared memory sections are coupled to each other by an inter-shared memory path, said selector applies an access request from one of said at least two processors to one of said two shared memory sections, said one shared memory section responds to the applied access request to perform an access process and sends a command to the other of said two shared memory sections, and the other shared memory section responds to the command to perform an access process.  
     
     
         4 . A storage control apparatus according to  claim 1 , wherein said shared memory unit includes a shared memory section serving as master and another shared memory section serving as slave, said shared memory sections being coupled to said selector and coupled to each other by an inter-shared memory path and having each an access circuit; 
 said selector has means for receiving an address, a write command and write data from one of said two processors when said one processor performs a write process to said shared memory unit and transmitting the received address, write command and write data to each of said shared memory sections;    said access circuit of said shared memory section serving as master has means for receiving said address, command and write data from said selector and writing said write data at said received address, and means for transmitting said received address to said shared memory section serving as slave through said inter-shared memory path; and    said access circuit of said shared memory section serving as slave has write means for responding to said address received through said inter-shared memory path to write said write data from said selector at said received address.    
     
     
         5 . A storage control apparatus according to  claim 4 , said access circuit of said shared memory section serving as slave further has means for comparing said address received through said inter-shared memory path with said address from said selector and delivering a coincidence output when said addresses coincide with each other, wherein said write means of said access circuit of the shared memory section serving as slave responds to the coincidence output to write said write data from said selector at said received address.  
     
     
         6 . A storage control apparatus according to  claim 1 , wherein said shared memory unit has a shared memory section serving as master and another shared memory section serving as slave, said shared memory sections being coupled to said selector and coupled to each other by an inter-shared memory path and having each an access circuit; 
 said selector has means for receiving an address and a read command from one of said two processors when said one processor performs a read process to said shared memory unit and transmitting said received address and read command to each of said two shared memory sections;    said access circuit of said shared memory section serving as master has means for receiving said address and read command from said selector and reading read data from the received address to transfer it to said selector, and means for transmitting said received address to said shared memory section serving as slave through said inter-shared memory path;    said access circuit of said shared memory section serving as slave has transfer means for responding to said address received through said inter-shared memory path to read out read data from said received address and transferring the read-out read data to said selector; and    said selector has means for comparing the read data received from said shared memory section serving as master with the read data received from said shared memory section serving as slave to deliver a read data coincidence output when both the data coincide with each other and responding to said read data coincidence output to transmit said read data to one of said two processors.    
     
     
         7 . A storage control apparatus according to  claim 6 , wherein said access circuit of said shared memory section serving as slave further has means for comparing said address received through said inter-shared memory path with said address from said selector and delivering an address coincidence output when said addresses coincide with each other, and said transfer means of said access circuit of said shared memory section serving as slave responds to the address coincidence output to read out read data from said received address and transfers it to said selector.  
     
     
         8 . A storage control apparatus according to  claim 1 , wherein said shared memory unit has a shared memory section serving as master and another shared memory section serving as slave, said shared memory sections being coupled to said selector and coupled to each other by an inter-shared memory path and having each an access circuit; 
 said selector has means for receiving an address, a write command and write data from one of said two processors when said one processor performs a write process to said shared memory unit and transmitting the received address, write command and write data to said shared memory section serving as master;    said access circuit of said shared memory section serving as master has means for receiving said address, write command and write data from said selector to write the write data at said received address, and means for transmitting said received address, write command and write data to said shared memory section serving as slave through said inter-shared memory path; and    said access circuit of said shared memory section serving as slave has means for responding to said address received through said inter-shared memory path to write said received data at said received address and means for transmitting a write end report to said shared memory section serving as master through said inter-shared memory path.    
     
     
         9 . A storage control apparatus according to  claim 1 , wherein said shared memory unit has a shared memory section serving as master and another shared memory section serving as slave, said shared memory sections being coupled to said selector and coupled to each other by an inter-shared memory path and having each an access circuit; 
 said selector has means for receiving an address and a read command from one of said two processors when said one processor performs a read process of said shared memory unit and transmitting the received address and read command to said shared memory section serving as master;    said access circuit of said shared memory section serving as master has means for receiving said address and read command from said selector to read out read data from said received address, and means for transmitting said received address and said received read command to said shared memory section serving as slave through said inter-shared memory path; and    said access circuit of said shared memory section serving as slave has transfer means for responding to said address received through said inter-shared memory path to read out read data from said received address and transferring the read-out read data to said shared memory section serving as master through said inter-shared memory path,    said access circuit of said shared memory section serving as master further having means for comparing the read data read out of said shared memory section serving as master with the read data received from said shared memory section serving as slave and delivering a read data coincidence output when both the read data coincide with each other, and means for responding to said read data coincidence output to transmit said read data and a read-out end report to said selector.    
     
     
         10 . A storage control apparatus according to  claim 1  further comprising: 
 means for determining first and second cashe addresses necessary for storing write data received from said central processing unit in first and second cashe memory sections in a dual fashion, respectively, and means for transmitting said first and second cashe addresses, a write command and write data to said selector,  
 wherein said selector has means for receiving from one of said two processors said first and second cashe addresses, write command and write data and transmitting said first cashe address, write command and write data TO SAID first cashe memory section corresponding to said first cashe address and said second cashe address, write command and write data to said second cashe memory section corresponding to said second cashe address;  
 said first cashe memory section stores the write data at said first cashe address received from said selector; and  
 said second cashe memory section stores the write data at said second cashe address received from said selector.  
 
     
     
         11 . A storage control apparatus according to  claim 1 , wherein said cashe memory unit includes first and second cashe memory sections coupled to said selector through access paths, respectively; and 
 one of said two processors has means for reading data from a first cashe address of said first cashe memory section serving as copy originator through said selector and writing said read-out data to a second cashe address of said second cashe memory section serving as copy destination through said selector.    
     
     
         12 . A storage control apparatus according to  claim 1 , wherein said cashe memory unit includes first and second cashe memory sections coupled to said selector through access paths, respectively; 
 one of said two processors has means for designating to said selector a command to designate copying of data from a first cashe address of said first cashe memory section serving as copy originator to a second cashe address of said second cashe memory section serving as copy destination; and    said selector has means for responding to said command to read data from said first cashe address of said first cashe memory section, and means for transferring the read-out data to said second cashe address of said second cashe memory section serving as copy destination.    
     
     
         13 . A storage control apparatus coupled to a central processing unit and a storage unit to control input/output of data between said central processing unit and said storage unit, comprising: 
 at least two processors coupled to said central processing unit and said storage unit, respectively;    a cashe memory unit for temporarily storing data of said storage unit;    a shared memory unit for storing information concerning control of said cashe memory unit and said storage unit;    a first selector coupled to said at least two processors and said shared memory unit through access paths, respectively, to selectively apply access requests from said at least two processors to said shared memory unit; and    a second selector coupled to said at least two processors and said cashe memory unit through access paths, respectively, to selectively apply access requests from said at least two processors to said cashe memory unit.    
     
     
         14 . A storage control apparatus coupled to a central processing unit and a storage unit to control input/output of data between said central processing unit and said storage unit, comprising: 
 at least two processors coupled to said central processing unit and said storage unit, respectively;    a cashe memory unit for temporarily storing data of said storage unit;    a shared memory unit for storing information concerning control of said cashe memory unit and said storage unit; and    two selectors each coupled to said at least two processors, said shared memory unit and said cashe memory unit through access paths and being operative to selectively apply access requests from said at least two processors to said shared memory unit or said cashe memory unit.    
     
     
         15 . A storage control apparatus according to  claim 14 , wherein each of said at least two processors has an access route to said shared memory unit and an access route to said cashe memory unit by way of one of said selectors and has an access route to said shared memory unit and an access route to said cashe memory unit by way of the other of said selectors, and each of said at least two processors has means for normally making all of said access routes usable and, when one of all the access routes becomes faulty, for using the remaining access routes exclusive of said one faulty access route.  
     
     
         16 . A storage control apparatus according to  claim 14 , wherein each of said at least two processors has means for determining the access routes from each of said at least two processors to said shared memory unit and said cashe memory unit.  
     
     
         17 . A storage control apparatus according to  claim 16 , wherein said access route determining means determines the access routes in accordance with an address to be accessed of said shared memory unit or an address to be accessed of said cashe memory unit.  
     
     
         18 . A storage control apparatus coupled to a central processing unit and a storage unit to control input/output of data between said central processing unit and said storage unit, comprising: 
 at least two processors coupled to said central processing unit and said storage unit;    a memory unit having a cashe memory area for temporarily storing data of said storage unit and a shared memory area for storing information concerning control of said cashe memory area and said storage unit; and    a selector coupled to said at least two processors and said memory unit, respectively, through access paths to apply access requests from said at least two processors to said memory unit.    
     
     
         19 . A storage control apparatus coupled to a central processing unit and a storage unit to control input/output of data between said central processing unit and said storage unit, comprising: 
 at least three processors coupled to said central processing unit and said storage unit;    two memory units each having a cashe memory area for temporarily storing data of said storage unit and a shared memory area for storing information concerning control of said cashe memory area and said storage unit; and    two selectors each coupled to said at least three processors and said two memory units through access paths and being operative to selectively apply access requests from said at least three processors to said two memory units.