Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device

Abstract

A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

What is claimed is:  
     
         1 . A method of manufacturing a semiconductor device, comprising the steps of: 
 (a) providing a semiconductor substrate with first conductor patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate and with grooves formed in self-alignment with said first conductor patterns in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that said grooves in said peripheral circuit region define an active region of an MISFET in said peripheral circuit region;    (b) burying a first insulating film in said grooves;    (c) forming a second conductor pattern over said first conductor patterns and said first insulating film;    (d) forming a second insulating film over said second conductor pattern;    (e) forming a conductive film over said second insulating film; and    (f) patterning said conductive film, said second conductor pattern and said first conductor patterns in said peripheral circuit region and in said memory cell forming region,    wherein, in said step (f), the conductive film, of said memory cell forming region, is patterned to form a control gate electrode of a memory cell,    wherein, in said step (f), said second conductor pattern and said first conductor pattern of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and    wherein, in said step (f), at least said second conductor pattern and the first conductor pattern of said peripheral circuit region are patterned to form a gate electrode of said MISFET in said peripheral circuit region.    
     
     
         2 . A method of manufacturing a semiconductor device according to  claim 1 , further comprising the step of: 
 (g) between said step (d) and said step (e), forming an opening in said second insulating film,    wherein, in said step (e), the conductive film, of said peripheral circuit region, is patterned so as to be electrically connected to said gate electrode of said MISFET through said opening.    
     
     
         3 . A method of manufacturing a semiconductor device according to  claim 1 , wherein, in said step (b), said first insulating film is comprised of a fluid silicon oxide film containing phosphorus or boron.  
     
     
         4 . A method of manufacturing a semiconductor device, comprising steps of: 
 (a) providing a semiconductor substrate with first conductor patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate and with grooves formed in self-alignment with said first conductor patterns in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that said grooves in said peripheral circuit region define an active region of an MISFET in said peripheral circuit region;    (b) burying a first insulating film in said grooves;    (c) forming a second insulating film over said first conductor patterns and said first insulating film;    (d) forming a conductive film over said second insulating film; and    (e) patterning said conductive film and said first conductor patterns in said memory cell forming region and in said peripheral circuit region,    wherein, in said step (e), the conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell,    wherein, in said step (e), the first conductor pattern of said memory cell forming region is patterned to form a floating gate electrode of said memory cell, and    wherein, in said step (e), at least the first conductor pattern of said peripheral circuit region is patterned to form a gate electrode of said MISFET in said peripheral circuit region.    
     
     
         5 . A method of manufacturing a semiconductor device according to  claim 4 , further comprising the step of: 
 (g) between said step (c) and said step (d), forming an opening in said second insulating film,    wherein, in said step (d), the conductive film of said peripheral circuit region is patterned so as to be electrically connected to said gate electrode of said MISFET through said opening.    
     
     
         6 . A method of manufacturing a semiconductor device, comprising steps of: 
 (a) forming first conductor patterns over a memory cell forming region and a peripheral circuit region of a semiconductor substrate;    (b) forming grooves, in self-alignment with said first conductor patterns, in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that said grooves in said peripheral circuit region define an active region of an MISFET in said peripheral circuit region;    (c) burying a first insulating film in said grooves;    (d) forming a second conductor pattern over said first conductor patterns and said first insulating film;    (e) forming a second insulating film over said second conductor pattern;    (f) forming a second conductive film over said second insulating film; and    (g) patterning said second conductive film, said second conductor pattern and said first conductor patterns in said memory cell forming region and in said peripheral circuit region,    wherein, in said step (g), said second conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell,    wherein, in said step (g), said first conductor patterns and said second conductor pattern of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and    wherein, in said step (g), at least said second conductor pattern and said first conductor patterns of said peripheral circuit region are patterned to form a gate electrode of said MISFET in said peripheral circuit region.    
     
     
         7 . A method of manufacturing a semiconductor device according to  claim 6 , wherein in said step (a) each of said first conductor patterns has a third insulating film formed thereover, 
 wherein in said step (b) said grooves are formed in self-alignment with said third insulating film over said first conductor patterns, and    wherein, before said step (c), said third insulating film is removed.    
     
     
         8 . A method of manufacturing a semiconductor device according to  claim 6 , further comprising the step of: 
 (h) between said step (f) and said step (g), forming an opening in said second insulating film,    wherein, in said step (g), the second conductive film, of said peripheral circuit region, is patterned so as to be electrically connected to said gate electrode of said MISFET through said opening.    
     
     
         9 . A method of manufacturing a semiconductor device, comprising steps of: 
 (a) forming first conductor patterns over a memory cell forming region and a peripheral circuit region of a semiconductor substrate;    (b) forming grooves, in self-alignment with said first conductor patterns, in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that said grooves in said peripheral circuit region define an active region of an MISFET in said peripheral circuit region;    (c) burying a first insulating film in said grooves;    (d) forming a second insulating film over said first conductor patterns and said first insulating film;    (e) forming a second conductive film over said second insulating film; and    (f) patterning said second conductive film and said first conductor patterns in said memory cell forming region and in said peripheral circuit region,    wherein, in said step (f), the second conductive film, of said memory cell forming region, is patterned to form a control gate electrode of a memory cell,    wherein, in said step (f), said first conductor pattern of said memory cell forming region is patterned to form a floating gate electrode of said memory cell, and    wherein, in said step (f), at least said first conductor pattern of said peripheral circuit region is patterned to form a gate electrode of said MISFET in said peripheral circuit region.    
     
     
         10 . A method of manufacturing a semiconductor device according to  claim 9 , wherein, in said step (a), each of said first conductor patterns includes a third insulating film formed over the first conductor pattern, 
 wherein, in said step (b), said grooves are formed in self-alignment with said third insulting film and said first conductor patterns, and    wherein, before said step (c), said third insulating film is removed.    
     
     
         11 . A method of manufacturing a semiconductor device according to  claim 9 , further comprising the step of: 
 (g) between said step (d) and said step (e), forming an opening in said second insulating film,    wherein, in said step (f), the second conductive film, of said peripheral circuit region, is patterned so as to be electrically connected to said gate electrode of said MISFET through said opening.