Multi-port packet processor

Abstract

A multi-port packet processor on an integrated circuit provides an efficient means to interface multiple high-speed packet-based communications channels. The multi-port packet processor includes multiple port processors. Each port processor can include a channel interface for coupling to a respective communications channel, a channel processor for processing the data packets received through the channel interface, and an interprocessor communications interface for providing communication between the port processors. The channel interface can be designed to process data packets using a particular set of packet-based protocols. Alternatively, the channel interface can be designed having programmable controls to allow processing of data packets using a selected set, from a number of possible sets, of packet-based protocols.

What is claimed is:  
     
         1 . A multi-port packet processor comprising: 
 more than one of port processors, each port processor comprising 
 a channel interface for coupling to at least one communications channel, and  
 a channel processor coupled to the channel interface, the channel processor processing data packets received or transmitted through the communications channel; and  
   wherein the port processors are implemented within one integrated circuit.    
     
     
         2 . The multi-port packet processor of  claim 1  further comprising: 
 more than one support circuit, one support circuit coupled to each of the port processors, wherein the support circuits facilitate communication with respective communications channels.  
 
     
     
         3 . The multi-port packet processor of  claim 2  wherein the support circuit of one or more of the port processors provides analog conversion circuitry for different physical signal states communicating bits on the coupled communication channel.  
     
     
         4 . The multi-port packet processor of  claim 1  wherein each port processor further comprises 
 an interprocessor communications interface coupled to the channel processor and the interprocessor communications interfaces to at least one other port processor.  
 
     
     
         5 . The multi-port packet processor of  claim 1  wherein the channel interface of at least one port processor supports more than one packet-based protocol.  
     
     
         6 . The multi-port packet processor of  claim 5  wherein the channel interface can be programmably reconfigured to process data packets using a selected protocol from a set of more than one packet-based protocol.  
     
     
         7 . The multi-port packet processor of  claim 5  wherein the processed packet-based protocols include at least one of an Integrated Services Data Network (ISDN), an Ethernet, a Fast Ethernet, a Gigabit Ethernet, an Asynchronous Transfer Mode (ATM), a Copper Distributed Data Interface (CDDI), a Fiber Distributed Data Interface (FDDI), a RS-485 GPIB, and a P1384.  
     
     
         8 . The multi-port packet processor of  claim 1  as used in a local area network.  
     
     
         9 . The multi-port packet processor of  claim 1  as used in a wide area network.  
     
     
         10 . The multi-port packet processor of  claim 1  as used in a disk storage environment.  
     
     
         11 . The multi-port packet processor of  claim 1  comprising four port processors.  
     
     
         12 . The multi-port packet processor of  claim 1  comprising eight port processors.  
     
     
         13 . The multi-port packet processor of  claim 1  wherein each port processor further includes a memory coupled to the channel processor.  
     
     
         14 . The multi-port packet processor of  claim 1  wherein the port processors are arranged in substantially rectangular strips possessing a short axis in the integrated circuit.  
     
     
         15 . The multi-port packet processor of  claim 14  wherein the port processors are flipped about the short axis for neighboring port processors.  
     
     
         16 . The multi-port packet processor of  claim 14  wherein the port processors are arranged as pairs of port processors wherein the pairs of adjacent port processors are flipped about the short axis for neighboring pairs of port processors.  
     
     
         17 . A local area network (LAN) processor comprising: 
 more than one port processors, each port processor coupled to a respective communications channel, each port processor providing packet-based processing using respective packet-based protocols;    wherein all of the port processors are implemented within one integrated circuit.    
     
     
         18 . The multi-port processor of  claim 1  wherein the port processors operate on packets at a physical layer.  
     
     
         19 . The multi-port processor of  claim 1  wherein the port processors further operate on packets at a data link layer.  
     
     
         20 . The multi-port processor of  claim 1  wherein the port processors further operate on packets at a network layer.  
     
     
         21 . The multi-port processor of  claim 1  wherein the channel interface of at least one of the port processors couples to more than one communications channel.  
     
     
         22 . A grid array processor comprising: 
 a more than one of multi-port packet processors arranged in a two-dimensional array, each multi-port packet processor coupled to at least one other multi-port packet processor, each multi-port packet processor including 
 a more than one of port processors, each port processor coupled to at least one respective communications channel, each port processor providing packet-based processing using respective packet-based protocols;  
 wherein each multi-port packet processor is implemented within one integrated circuit.  
   
     
     
         23 . A multi-dimensional grid array processor comprising: 
 more than one of multi-port packet processors arranged in a multi-dimensional array, each multi-port packet processor coupled to at least one other multi-port packet processor, each multi-port packet processor including 
 more than one port processors, each port processor coupled to at least one respective communications channel, each port processor providing packet-based processing using respective packet-based protocols;  
 wherein each multi-port packet processor is implemented in one integrated circuit.