High-gain PNP bipolar junction transistor in CMOS device and method for forming the same

Abstract

An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

What is claimed is:  
     
         1 . An integrated circuit device, comprising: 
 a semiconductor substrate;    a first n-well in said substrate;    a first p-well contiguous with said first n-well in said substrate;    a second n-well contiguous with said first p-well including    a second p-well having a first n-type region and a second n-type region, said first and second n-type regions respectively defining emitter and collector regions of a first BJT, and    a first p-type region spaced apart from said second p-well, said first p-type region and said second p-well respectively defining emitter and collector regions of a second BJT.    
     
     
         2 . The integrated circuit device as claimed in  claim 1 , further comprising a third n-type region spaced apart from said first p-type region.  
     
     
         3 . The integrated circuit device as claimed in  claim 1 , wherein said first n-type region is a collector of a composite pnp BJT.  
     
     
         4 . The integrated circuit device as claimed in  claim 1 , wherein said second n-type region and said first p-type region comprise emitter of a composite pnp BJT.  
     
     
         5 . The integrated circuit device as claimed in  claim 1 , wherein said third n-type region is a base of a composite pnp BJT.  
     
     
         6 . The integrated circuit device as claimed in  claim 1 , wherein said first p-type region and said third n-type region are separated by a shallow trench isolation.  
     
     
         7 . The integrated circuit device as claimed in  claim 1 , wherein said second p-well comprises an npn BJT.  
     
     
         8 . The integrated circuit device as claimed in  claim 1 , wherein said second p-well, said first p-type region, and said third n-type region comprise a pnp BJT.  
     
     
         9 . The integrated circuit device as claimed in  claim 1 , wherein said second p-well having said first n-type region and said second n-type region comprises an npn BJT having a first gain, and said second p-well, said first p-type region, and said third n-type region comprise a pnp BJT having a second gain, and wherein said npn BJT and said pnp BJT together form a composite pnp BJT having a combined gain equal to a product of said first gain multiplied by said second gain.  
     
     
         10 . The integrated circuit device as claimed in  claim 9 , wherein said combined gain may be controlled by the gate lengths of said npn BJT and said pnp BJT.  
     
     
         11 . An integrated circuit device, comprising: 
 a semiconductor substrate;    an NMOS formed in said substrate;    a PMOS contiguous with said NMOS and formed in said substrate; and    a composite pnp bipolar junction transistor contiguous with said NMOS and formed in said substrate, said composite pnp bipolar junction transistor including: 
 a lateral npn bipolar junction transistor having first and second spaced-apart n-type regions, and  
 a lateral pnp bipolar junction transistor including said second spaced-apart n-type region, a first spaced-apart p-type region and a third n-type region, wherein said first p-type spaced-apart region and said third n-type region are separated by a shallow trench isolation.  
   
     
     
         12 . The integrated circuit device as claimed in  claim 11 , wherein said first n-type spaced-apart region is a collector of said composite pnp bipolar junction transistor.  
     
     
         13 . The integrated circuit device as claimed in  claim 11 , wherein said second n-type spaced-apart region and said first p-type spaced-apart region comprise an emitter of said composite pnp bipolar junction transistor.  
     
     
         14 . The integrated circuit device as claimed in  claim 11 , wherein said third n-type region is a base of said composite pnp bipolar junction transistor.  
     
     
         15 . The integrated circuit device as claimed in  claim 11 , wherein a gain of said composite pnp bipolar junction transistor equals a gain of said lateral npn bipolar junction transistor multiplied by a gain of said lateral pnp bipolar junction transistor.  
     
     
         16 . An integrated circuit device, comprising: 
 a semiconductor substrate;    an NMOS formed in said substrate;    a PMOS contiguous with said NMOS and formed in said substrate; and    a composite pnp bipolar junction transistor contiguous with said NMOS and formed in said substrate, said composite pnp bipolar junction transistor including: 
 a lateral npn bipolar junction transistor having a first current gain, and  
 a lateral pnp bipolar junction transistor having a second current gain,  
   wherein a current gain of said composite pnp bipolar junction transistor equals said first current gain multiplied by said second current gain.    
     
     
         17 . A method for forming a composite pnp BJT in a CMOS device having a substrate including an n-well region, comprising: 
 providing a first photoresist over said substrate;    patterning and defining said photoresist to expose a portion above said n-well region;    implanting said n-well region with a dopant to form a shallow p-well region;    removing said photoresist;    implanting a first dose of dopant to form lightly-doped n-type spaced-apart regions;    implanting a second dose of dopant to form a lightly-doped p-type spaced-apart region;    forming a gate structure including a gate and gate oxide;    implanting a third dose of dopant into said lightly-doped spaced-apart n-type regions to form heavily-doped n-type regions, said third dose of dopant being more concentrated than said first dose of dopant; and    implanting a fourth dose of dopant into said lightly-doped spaced-apart p-type region to form a heavily-doped p-type region, said fourth dose of dopant being higher concentration than said second dose of dopant.    
     
     
         18 . The method as claimed in  claim 17 , wherein said implanting of said n-well region with a dopant comprises a step of implanting a dopant having a dose of approximately 10 11  to 5×10 13  per cm 2  at an energy of approximately between 60 KeV to 120 KeV.