Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof

Abstract

A high electron mobility transistor has a channel layer overlain by an electron supply layer held in contact with a gate electrode, and source/drain electrodes form ohmic contact together with cap layers, and resistive etching stopper are inserted between the cap layers and the electron supply layers for preventing the electron supply layer from over-etching, wherein extremely thin delta-doped layers are formed between the etching stopper layers and the electron supply layer so that the resistance between the electron supply layer and the source/drain electrodes are reduced.

What is claimed is:  
     
         1 . A compound semiconductor device fabricated on a substrate, comprising: 
 a multiple-layered structure including an active layer;    plural cap layers respectively located over plural portions of said active layer;    plural highly-resistive layers formed between said multiple-layered structure and said plural cap layers so as to form a recess located over a part of said multiple-layered structure and between said plural cap layers;    plural delta-doped layers formed between said plural highly-resistive layers and said multiple-layered structure for decreasing potential barriers of said plural highly-resistive layers;    a first electrode held in contact with said part of said multiple-layered structure for controlling the amount of current flowing through said active layer; and    second electrodes respectively formed on said plural cap layers for providing current paths from and to said active layer through said plural cap layers, said plural highly-resistive layers and said plural delta-doped layers.    
     
     
         2 . The compound semiconductor device as set forth in  claim 1 , in which said plural delta-doped layers are thin so that a tunneling phenomenon takes place.  
     
     
         3 . The compound semiconductor device as set forth in  claim 1 , in which the thickness of said plural delta-doped layers is equal to a single atom to several atoms.  
     
     
         4 . The compound semiconductor device as set forth in  claim 1 , in which said plural delta doped layers contain only one kind of dopant impurity.  
     
     
         5 . The compound semiconductor device as set forth in  claim 1 , in which said active layer has a conductive channel layer for said current.  
     
     
         6 . The compound semiconductor device as set forth in  claim 5 , in which said active layer further has a carrier supply layer for producing an inversion layer at the boundary between said carrier supply layer and said conductive channel layer.  
     
     
         7 . The compound semiconductor device as set forth in  claim 6 , in which said carrier supply layer has a large dopant concentration in a first portion close to the boundary formed with said channel layer and a small dopant concentration in a second portion close to said gate electrode.  
     
     
         8 . The compound semiconductor device as set forth in  claim 1 , in which said plural highly-resistive layers serve as an etching stopper for preventing said active layer from an etchant used for patterning said plural cap layers.  
     
     
         9 . The compound semiconductor device as set forth in  claim 1 , in which said plural highly-resistive layers are formed of undoped compound semiconductor.  
     
     
         10 . A process for fabricating a compound semiconductor device, comprising the steps of: 
 a) producing a multiple-layered structure having an active layer, a delta-doped layer over said active layer, a highly resistive layer over said delta-doped layer and a highly conductive layer over said delta-doped layer on a semi-insulating substrate;    b) removing a part of said highly conductive layer so as to expose a part of said highly resistive layer to a first opening formed between remaining portions of said highly conductive layer serving as plural can layers;    c) removing said part of said highly resistive layer and a part of said delta-doped layer thereunder so as to expose a part of said active layer to a second opening formed between plural delta doped layers respectively overlain by highly resistive layers; and    d) completing a compound semiconductor device having a first electrode held in contact with said part of said active layer and second electrodes respectively held in contact with said plural cap layers.    
     
     
         11 . The process as set forth in  claim 10 , in which said highly resistive layer serves as an etching stopper carried out in said step b) so as to prevent said active layer from a first etchant.  
     
     
         12 . The process as set forth in  claim 11 , in which step b) includes the sub-steps of 
 b-1) forming an etching mask on said highly conductive layer, and    b-2) exposing said highly conductive layer to said first etchant having a large selectivity to a first kind of compound semiconductor forming said highly conductive layer with respect to a second kind of compound semiconductor forming said highly resistive layer.    
     
     
         13 . The process as set forth in  claim 12 , in which said first etchant contains an oxidizing agent for producing an oxide from said second kind of compound semiconductor.  
     
     
         14 . The process as set forth in  claim 13 , in which a second etchant is used for removing said oxide and said part of said delta-doped layer, and has a large selectivity to said oxide and said delta-doped layer with respect to a third kind of compound semiconductor forming said active layer.  
     
     
         15 . The process as set forth in  claim 13 , in which said oxidizing agent is hydrogen peroxide, and said first kind of compound semiconductor and said second kind of compound semiconductor contain a negligible amount of aluminum and a large amount of aluminum, respectively.  
     
     
         16 . The process as set forth in  claim 15 , in which said first etchant further contains citric acid, and said first kind of compound semiconductor and said second kind of compound semiconductor are gallium arsenide and aluminum gallium arsenide, respectively.  
     
     
         17 . The process as set forth in  claim 10 , in which said step b) includes the sub-steps of 
 b-1) depositing an oxide over said highly conductive layer for forming an oxide layer,    b-2) partially removing said oxide layer for forming an etching mask, and    b-3) etching said part of said highly conductive layer by using said etching mask.    
     
     
         18 . The process as set forth in  claim 17 , in which said etching mask serves as a protective layer surrounding said first electrode.