Method of forming a floating gate of a non-volatile memory device

Abstract

A method of forming a floating gate of a non-volatile memory device is disclosed. First, a gate dielectric layer and a first polysilicon layer are formed on a semiconductor substrate. After forming a first dielectric layer on the first polysilicon layer, the first dielectric layer is patterned to form an opening. After that, a recess with sloped sidewalls is formed in the first polysilicon layer by partially etching the first polysilicon layer through the opening. Next, a top silicon oxide is formed by performing a thermal oxidation process. After removing the first dielectric layer, a floating gate with sharp corners is formed by performing an anisotropical etching process to etch an exposed portion of the first polysilicon layer using the top silicon oxide as an etching mask.

What we claimed is:  
     
         1 . A method of forming a floating gate of a non-volatile memory device, said method comprising: 
 a. forming a gate dielectric layer and a first polysilicon layer on a semiconductor substrate;    b. forming a first dielectric layer on said first polysilicon layer;    c. patterning said first dielectric layer to form an opening;    d. forming a recess with sloped sidewalls in said first polysilicon layer by partially etching said first polysilicon layer through said opening;    e. forming a top silicon oxide by performing a thermal oxidation process;    f. removing said first dielectric layer; and    g. forming said floating gate with sharp corners by performing an anisotropical etching process to etch an exposed portion of said first polysilicon layer using said top silicon oxide as an etching mask.    
     
     
         2 . The method of  claim 1 , after forming said first polysilicon layer, further comprising forming a buffer layer on said first polysilicon layer.  
     
     
         3 . The method of  claim 2 , wherein said buffer layer is composed of silicon oxide.  
     
     
         4 . The method of  claim 1 , wherein said first dielectric layer is composed of silicon nitride.  
     
     
         5 . The method of  claim 1 , wherein said first dielectric layer is composed of silicon oxynitride.  
     
     
         6 . The method of  claim 1 , wherein said gate dielectric layer is composed of silicon nitride.  
     
     
         7 . The method of  claim 1 , wherein said gate dielectric layer is composed of silicon oxynitride.  
     
     
         8 . The method of  claim 1 , wherein said recess with sloped sidewalls in said first polysilicon layer is formed by partially etching said first polysilicon layer through said opening by means of a wet etching step.  
     
     
         9 . The method of  claim 1 , wherein said recess with sloped sidewalls in said first polysilicon layer is formed by partially etching said first polysilicon layer through said opening by means of a dry etching step.  
     
     
         10 . The method of  claim 1 , wherein said sidewalls of said recess have a slope ranged from 40 to 80 degree with respect to a horizontal plane.  
     
     
         11 . The method of  claim 1 , wherein said first dielectric layer is removed by performing a wet etching process using hot phosphoric acid.  
     
     
         12 . The method of  claim 1 , after forming said floating gate further comprising: 
 a. forming a tunneling dielectric layer over said floating gate; and    b. forming a control gate of said non-volatile memory cell on said tunneling dielectric layer.    
     
     
         13 . The method of  claim 12 , wherein said tunneling dielectric layer is formed by first depositing a dielectric layer and then patterning said dielectric layer by conventional photolithography process and etching process.  
     
     
         14 . The method of  claim 13 , wherein said dielectric layer is an oxide/nitride composition film.  
     
     
         15 . The method of  claim 13 , wherein said dielectric layer is an oxide/nitride/oxide composition film (ONO).  
     
     
         16 . The method of  claim 12 , wherein said control gate is formed by first depositing a second polysilicon layer and then patterning said second polysilicon layer.  
     
     
         17 . A method of forming a gate structure with sharp corners, said method comprising: 
 a. forming a gate dielectric layer and a polysilicon layer on a semiconductor substrate;    b. forming a first dielectric layer on said polysilicon layer;    c. patterning said first dielectric layer to form an opening;    d. forming a recess with sloped sidewalls in said polysilicon layer by partially etching said polysilicon layer through said opening;    e. forming a top silicon oxide by performing a thermal oxidation process;    f. removing said first dielectric layer; and    g. forming said gate structure with sharp corners by performing an anisotropical etching process to etch an exposed portion of said polysilicon layer using said top silicon oxide as an etching mask.    
     
     
         18 . The method of  claim 17 , wherein said recess with sloped sidewalls in said polysilicon layer is formed by partially etching said polysilicon layer through said opening by means of a dry etching step.  
     
     
         19 . The method of  claim 17 , wherein said sidewalls of said recess have a slope ranged from 40 to 80 degree with respect to a horizontal plane.  
     
     
         20 . The method of  claim 17 , wherein said first dielectric layer is removed by performing a wet etching process using hot phosphoric acid.