Polysilicon microelectronic reflectors and beams and methods of fabricating same

Abstract

A microelectronic reflector is fabricated by forming a first polysilicon layer on a microelectronic substrate, forming a first phosphosilicate glass (PSG) layer on the first polysilicon layer, and reactive ion etching to remove the first PSG layer from at least a portion of the first polysilicon layer. A second polysilicon layer is formed on at least a portion of the first polysilicon layer from which the first PSG layer was removed and a second PSG layer is formed on at least a second portion of the second polysilicon layer. Reactive ion etching is performed to remove the second PSG layer from at least a portion of the second polysilicon layer. A third PSG layer then is formed on at least a portion of the second polysilicon layer from which the second PSG layer was removed. Reactive ion etching is performed to remove the third PSG layer from at least a portion of the second polysilicon layer. By forming a third PSG layer, and reactive ion etching this layer, additional stress may be created in the first and/or second doped polysilicon layers that bends the ends of the doped first and/or second polysilicon layers towards the microelectronic substrate upon release of the treated polysilicon layer from the substrate, compared to doped polysilicon layers on which the third PSG layer was not formed and reactive ion etched. This increased stress may be counteracted by forming a stress-correcting layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed, and then forming a reflective layer such as gold on at least a portion of the stress-correcting layer. The stress-correcting layer preferably comprises platinum, which can produce high stresses that can counteract the stresses in the first and second doped polysilicon layers, to thereby allow a flat mirror and/or beam to be produced.

What is claimed is:  
     
         1 . A method of fabricating a microelectronic reflector comprising: 
 forming a first polysilicon layer on a microelectronic substrate;    forming a first phosphosilicate glass (PSG) layer on the first polysilicon layer;    reactive ion etching to remove the first PSG layer from at least a portion of the first polysilicon layer;    forming a second polysilicon layer on at least a portion of the first polysilicon layer from which the first PSG layer was removed;    forming a second PSG layer on at least a portion of the second polysilicon layer;    reactive ion etching to remove the second PSG layer from at least a portion of the second polysilicon layer;    forming a third PSG layer on at least a portion of the second polysilicon layer from which the second PSG layer was removed;    reactive ion etching to remove the third PSG layer from at least a portion of the second polysilicon layer; and    forming a reflective layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed.    
     
     
         2 . A method according to  claim 1  wherein the following steps are performed between the steps of reactive ion etching to remove the first PSG layer from at least a portion of the first polysilicon layer and forming a second polysilicon layer on at least a portion of the first polysilicon layer from which the first PSG layer was removed: 
 forming a fourth PSG layer on the first polysilicon layer; and  
 reactive ion etching to remove the fourth PSG layer from at least a portion of the first polysilicon layer.  
 
     
     
         3 . A method according to  claim 1:   wherein the step of forming a first PSG layer comprises the step of annealing the first PSG layer;    wherein the step of forming a second PSG layer comprises the step of annealing the second PSG layer; and    wherein the step of forming a third PSG layer comprises the step of annealing the third PSG layer.    
     
     
         4 . A method according to  claim 1  wherein the steps of reactive ion etching comprise reactive ion etching with freon.  
     
     
         5 . A method according to  claim 1  wherein the step of forming a reflective layer comprises the step of forming a reflective layer comprising gold on at least a portion of the second polysilicon layer from which the third PSG layer was removed.  
     
     
         6 . A method according to  claim 5  wherein the following step is performed between the steps of reactive ion etching to remove the third PSG layer and forming a reflective layer comprising gold: 
 forming a stress-correcting layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed; and  
 wherein the step of forming a reflective layer comprising gold comprises forming a reflective layer comprising gold on at least a portion of the stress-correcting layer.  
 
     
     
         7 . A method according to  claim 6  wherein the following step is performed between the steps of reactive ion etching to remove the third PSG layer and forming a stress-correcting layer: 
 forming an adhesion-promoting layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed; and  
 wherein the step of forming a stress-correcting layer comprises forming a stress-correcting layer on at least a portion of the adhesion-promoting layer.  
 
     
     
         8 . A method according to  claim 6  wherein the stress-correcting layer comprises platinum.  
     
     
         9 . A method according to  claim 7  wherein the stress-correcting layer comprises platinum and wherein the adhesion-promoting layer comprises titanium or chromium.  
     
     
         10 . A method according to  claim 1  wherein the first polysilicon layer is thicker than the second polysilicon layer.  
     
     
         11 . A method according to  claim 5  wherein the following step is performed between the steps of reactive ion etching to remove the third PSG layer and forming a reflective layer comprising gold: 
 forming a platinum layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed; and  
 wherein the step of forming a reflective layer comprising gold comprises forming a reflective layer comprising gold on at least a portion of the platinum layer.  
 
     
     
         12 . A method according to  claim 11  wherein the following step is performed between the steps of reactive ion etching to remove the third PSG layer and forming a platinum layer: 
 forming a titanium or chromium layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed; and  
 wherein the step of forming a platinum layer comprises forming a platinum layer on at least a portion of the titanium or chromium layer.  
 
     
     
         13 . A method according to  claim 12  wherein the titanium or chromium layer is about 50 Å thick, wherein the platinum layer is at least about 200 Å thick and wherein the gold layer is about 50 Å thick.  
     
     
         14 . A method according to  claim 12  wherein the platinum layer is a least twice as thick as the sum of the thicknesses of the titanium or chromium layer and the gold layer.  
     
     
         15 . A method of fabricating a microelectronic reflector comprising: 
 forming a first polysilicon layer on a microelectronic substrate;    forming a first polysilicon doping layer on the first polysilicon layer;    removing the first polysilicon doping layer from at least a portion of the first polysilicon layer;    forming a second polysilicon layer on at least a portion of the first polysilicon layer from which the first polysilicon doping layer was removed;    forming a second polysilicon doping layer on at least a portion of the second polysilicon layer;    removing the second polysilicon doping layer from at least a portion of the second polysilicon layer;    forming a third polysilicon doping layer on at least a portion of the second polysilicon layer from which the second polysilicon doping layer was removed;    removing the third polysilicon doping layer from at least a portion of the second polysilicon layer; and    forming a reflective layer on at least a portion of the second polysilicon layer from which the third polysilicon doping layer was removed.    
     
     
         16 . A method according to  claim 15  wherein the following steps are performed between the steps of removing the first polysilicon doping layer from at least a portion of the first polysilicon layer and forming a second polysilicon layer on at least a portion of the first polysilicon layer from which the first polysilicon doping layer was removed: 
 forming a fourth polysilicon doping layer on the first polysilicon layer; and  
 removing the fourth polysilicon doping layer from at least a portion of the first polysilicon layer.  
 
     
     
         17 . A method according to claim  15 : 
 wherein the step of forming a first polysilicon doping layer comprises the step of annealing the first polysilicon doping layer;    wherein the step of forming a second polysilicon doping layer comprises the step of annealing the second polysilicon doping layer; and    wherein the step of forming a third polysilicon doping layer comprises the step of annealing the third polysilicon doping layer.    
     
     
         18 . A method according to  claim 15  wherein the steps of reactive ion etching comprise reactive ion etching with freon.  
     
     
         19 . A method according to  claim 15  wherein the step of forming a reflective layer comprises the step of forming a reflective layer comprising gold on at least a portion of the second polysilicon layer from which the third polysilicon doping layer was removed.  
     
     
         20 . A method according to  claim 19  wherein the following step is performed between the steps of removing the third polysilicon doping layer and forming a reflective layer comprising gold: 
 forming a stress-correcting layer on at least a portion of the second polysilicon layer from which the third polysilicon doping layer was removed; and  
 wherein the step of forming a reflective layer comprising gold comprises forming a reflective layer comprising gold on at least a portion of the stress-correcting layer.  
 
     
     
         21 . A method according to  claim 20  wherein the following step is performed between the steps of removing the third polysilicon doping layer and forming a stress-correcting layer: 
 forming an adhesion-promoting layer on at least a portion of the second polysilicon layer from which the third polysilicon doping layer was removed; and  
 wherein the step of forming a stress-correcting layer comprises forming a stress-correcting layer on at least a portion of the adhesion-promoting layer.  
 
     
     
         22 . A method according to  claim 20  wherein the stress-correcting layer comprises platinum.  
     
     
         23 . A method according to  claim 21  wherein the stress-correcting layer comprises platinum and wherein the adhesion-promoting layer comprises titanium or chromium.  
     
     
         24 . A method according to  claim 15  wherein the first polysilicon layer is thicker than the second polysilicon layer.  
     
     
         25 . A method according to  claim 19  wherein the following step is performed between the steps of removing the third polysilicon doping layer and forming a reflective layer comprising gold: 
 forming a platinum layer on at least a portion of the second polysilicon layer from which the third polysilicon doping layer was removed; and  
 wherein the step of forming a reflective layer comprising gold comprises forming a reflective layer comprising gold on at least a portion of the platinum layer.  
 
     
     
         26 . A method according to  claim 25  wherein the following step is performed between the steps of removing the third polysilicon doping layer and forming a platinum layer: 
 forming a titanium or chromium layer on at least a portion of the second polysilicon layer from which the third polysilicon doping layer was removed; and  
 wherein the step of forming a platinum layer comprises forming a platinum layer on at least a portion of the titanium or chromium layer.  
 
     
     
         27 . A method according to  claim 26  wherein the titanium or chromium layer is about 50 Å thick, wherein the platinum layer is at least about 200 Å thick and wherein the gold layer is about 50 Å thick.  
     
     
         28 . A method according to  claim 26  wherein the platinum layer is a least twice as thick as the sum of the thicknesses of the titanium or chromium layer and the gold layer.  
     
     
         29 . A method of fabricating a microelectronic reflector comprising: 
 forming a doped polysilicon base on a microelectronic substrate;    forming a metal stress-correcting layer on at least a portion of the doped polysilicon base; and    forming a metal reflective layer on at least a portion of the stress-correcting layer.    
     
     
         30 . A method according to  claim 29  wherein the following step is performed between the steps of forming a doped polysilicon base and forming a metal stress-correcting layer: 
 forming a metal adhesion-promoting layer on the doped polysilicon base; and  
 wherein the step of forming a metal stress-correcting layer comprises forming a metal stress-correcting layer on the metal adhesion-promoting layer.  
 
     
     
         31 . A method according to  claim 29  wherein the metal reflective layer comprises gold.  
     
     
         32 . A method according to  claim 31  wherein the metal stress-correcting layer comprises platinum.  
     
     
         33 . A method according to  claim 29  wherein the metal stress-correcting layer is at least four times as thick as the metal reflective layer.  
     
     
         34 . A method according to claim  30 : 
 wherein the metal reflective layer comprises gold;    wherein the metal stress-correcting layer comprises platinum; and    wherein the metal adhesion-promoting layer comprises titanium or chromium.    
     
     
         35 . A method according to  claim 34  wherein the titanium or chromium layer is about 50 Å thick, wherein the platinum layer is at least about 200 Å thick and wherein the gold layer is about 50 Å thick.  
     
     
         36 . A method according to  claim 34  wherein the platinum layer is a least twice as thick as the sum of the titanium or chromium layer and the gold layer.  
     
     
         37 . A method according to claim  29 : 
 wherein the step of forming a doped polysilicon base comprises the steps of: 
 forming a doped polysilicon layer on a microelectronic substrate; and  
 treating the doped polysilicon layer to create stress therein that bends the ends of the polysilicon layer towards the microelectronic substrate upon release of the treated polysilicon layer from the substrate, compared to absence of the treating step; and  
   wherein the step of forming a metal stress-correcting layer comprises forming a metal stress-correcting layer that has stress therein that counters the stress in the treated doped polysilicon base.    
     
     
         38 . A method according to  claim 37  wherein the step of forming a metal stress-correcting layer is followed by the step of releasing the polysilicon base from the substrate to form a microelectronic reflector that is planar.  
     
     
         39 . A microelectronic reflector, comprising: 
 a microelectronic substrate;    a doped polysilicon base that is spaced apart from the microelectronic substrate;    a metal stress-correcting layer on the doped polysilicon base, opposite the substrate; and    a metal reflective layer on the metal stress-correcting layer.    
     
     
         40 . A reflector according to  claim 39  wherein the doped polysilicon base comprises a phosphorous doped polysilicon layer.  
     
     
         41 . A reflector according to  claim 39  further comprising a metal adhesion-promoting layer between the doped polysilicon base and the metal stress-correcting layer.  
     
     
         42 . A reflector according to  claim 39  wherein the metal reflective layer comprises gold.  
     
     
         43 . A reflector according to  claim 42  wherein the metal stress-correcting layer comprises platinum.  
     
     
         44 . A reflector according to claim  41 : 
 wherein the metal reflective layer comprises gold;    wherein the metal stress-correcting layer comprises platinum; and    wherein the metal adhesion-promoting layer comprises titanium or chromium.    
     
     
         45 . A reflector according to  claim 44  wherein the titanium or chromium layer is about 50 Å thick, wherein the platinum layer is at least about 200 Å thick and wherein the gold layer is about 50 Å thick.  
     
     
         46 . A reflector according to  claim 44  wherein the platinum layer is a least twice as thick as the sum of the thicknesses of the titanium or chromium layer and the gold layer.  
     
     
         47 . A reflector according to claim  39 : 
 wherein the polysilicon base has a first stress therein; and    wherein the metal stress-correcting layer has a second stress therein that is equal and opposite the first stress.    
     
     
         48 . A microelectronic reflector, comprising: 
 a microelectronic substrate;    a doped polysilicon base that is spaced apart from the microelectronic substrate;    a platinum layer on the doped polysilicon base, opposite the substrate; and    a gold layer on the platinum layer.    
     
     
         49 . A reflector according to  claim 48  wherein the doped polysilicon base comprises a phosphorous doped polysilicon layer.  
     
     
         50 . A reflector according to  claim 49  further comprising a titanium or chromium layer between the doped polysilicon base and the platinum layer.  
     
     
         51 . A reflector according to  claim 50  wherein the titanium or chromium layer is about 50 Å thick, wherein the platinum layer is at least about 200 Å thick and wherein the gold layer is about 50 Å thick.  
     
     
         52 . A reflector according to  claim 50  wherein the platinum layer is a least twice as thick as the sum of the thicknesses of titanium or chromium layer and the gold layer.  
     
     
         53 . A method of fabricating a microelectronic beam comprising: 
 forming a first polysilicon layer on a microelectronic substrate;    forming a first phosphosilicate glass (PSG) layer on the first polysilicon layer;    reactive ion etching to remove the first PSG layer from at least a portion of the first polysilicon layer;    forming a second polysilicon layer on at least a portion of the first polysilicon layer from which the first PSG layer was removed;    forming a second PSG layer on at least a portion of the second polysilicon layer;    reactive ion etching to remove the second PSG layer from at least a portion of the second polysilicon layer;    forming a third PSG layer on at least a portion of the second polysilicon layer from which the second PSG layer was removed;    reactive ion etching to remove the third PSG layer from at least a portion of the second polysilicon layer; and    forming a metal layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed.    
     
     
         54 . A method according to  claim 53  wherein the following steps are performed between the steps of reactive ion etching to remove the first PSG layer from at least a portion of the first polysilicon layer and forming a second polysilicon layer on at least a portion of the first polysilicon layer from which the first PSG layer was removed: 
 forming a fourth PSG layer on the first polysilicon layer; and  
 reactive ion etching to remove the fourth PSG layer from at least a portion of the first polysilicon layer.  
 
     
     
         55 . A method according to claim  53 : 
 wherein the step of forming a first PSG layer comprises the step of annealing the first PSG layer;    wherein the step of forming a second PSG layer comprises the step of annealing the second PSG layer; and    wherein the step of forming a third PSG layer comprises the step of annealing the third PSG layer.    
     
     
         56 . A method according to  claim 53  wherein the step of forming a metal layer comprises: 
 forming a metal stress-correcting layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed.  
 
     
     
         57 . A method according to  claim 56  wherein the following step is performed between the steps of reactive ion etching to remove the third PSG layer and forming a stress-correcting layer: 
 forming a metal adhesion-promoting layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed; and  
 wherein the step of forming a metal stress-correcting layer comprises forming a metal stress-correcting layer on at least a portion of the metal adhesion-promoting layer.  
 
     
     
         58 . A method according to  claim 56  wherein the metal stress-correcting layer comprises platinum.  
     
     
         59 . A method according to  claim 57  wherein the metal stress-correcting layer comprises platinum and wherein the metal adhesion-promoting layer comprises titanium or chromium.  
     
     
         60 . A method according to  claim 53  wherein the step of forming a metal layer comprises: 
 forming a platinum layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed.  
 
     
     
         61 . A method according to  claim 60  wherein the following step is performed between the steps of reactive ion etching to remove the third PSG layer and forming a platinum layer: 
 forming a titanium or chromium layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed; and  
 wherein the step of forming a platinum layer comprises forming a platinum layer on at least a portion of the titanium or chromium layer.  
 
     
     
         62 . A method according to  claim 61  wherein the titanium or chromium layer is about 50 Å thick and wherein the platinum layer is at least about 200 Å thick.  
     
     
         63 . A method of fabricating a microelectronic beam comprising: 
 forming a doped polysilicon base on a microelectronic substrate;    forming a metal adhesion-promoting layer on at least a portion of the doped polysilicon layer; and    forming a metal stress-correcting layer on at least a portion of the metal adhesion-promoting layer.    
     
     
         64 . A method according to claim  63 : 
 wherein the metal stress-correcting layer comprises platinum; and    wherein the metal adhesion-promoting layer comprises titanium or copper.    
     
     
         65 . A method according to  claim 64  wherein the titanium or chromium layer is about 50 Å thick and wherein the platinum layer is at least about 200 Å thick.  
     
     
         66 . A method according to claim  63 : 
 wherein the step of forming a doped polysilicon base comprises the steps of: 
 forming a doped polysilicon layer on a microelectronic substrate; and  
 treating the doped polysilicon layer to create stress therein that bends the ends of the polysilicon layer towards the microelectronic substrate upon release of the treated polysilicon layer from the substrate, compared to absence of the treating step; and  
   wherein the step of forming a metal stress-correcting layer comprises forming a metal stress-correcting layer that has stress therein that counters the stress in the treated doped polysilicon base.    
     
     
         67 . A method according to  claim 66  wherein the step of forming a metal stress-correcting layer is followed by the step of releasing the polysilicon base from the substrate to form a microelectronic reflector that is planar.  
     
     
         68 . A microelectronic beam, comprising: 
 a microelectronic substrate;    a doped polysilicon base that is spaced apart from the microelectronic substrate;    a metal adhesion-promoting correcting layer on the doped polysilicon base, opposite the substrate; and    a metal stress-correcting layer on the metal adhesion-promoting layer.    
     
     
         69 . A beam according to  claim 68  wherein the doped polysilicon base comprises a phosphorous doped polysilicon layer.  
     
     
         70 . A beam according to claim  68 : 
 wherein the metal stress-correcting layer comprises platinum; and    wherein the metal adhesion-promoting layer comprises titanium or chromium.    
     
     
         71 . A beam according to claim  70  wherein the titanium or chromium layer is about 50 Å thick and wherein the platinum layer is at least about 200 Å thick.  
     
     
         72 . A beam according to claim  68 : 
 wherein the polysilicon base has a first stress therein; and    wherein the metal stress-correcting layer has a second stress therein that is equal and opposite the first stress.    
     
     
         73 . A microelectronic beam, comprising: 
 a microelectronic substrate;    a doped polysilicon base that is spaced apart from the microelectronic substrate;    a titanium or chromium layer on the doped polysilicon base, opposite the substrate; and    a platinum layer on the titanium or chromium layer.    
     
     
         74 . A beam according to claim  73  wherein the doped polysilicon base comprises a phosphorous doped polysilicon layer.  
     
     
         75 . A beam according to claim  73  wherein the titanium or chromium layer is about 50 Å thick and wherein the platinum layer is at least about 200 Å thick.