Structure of a low-voltage channel write/erase flash memory cell and fabricating method thereof

Abstract

The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which structure comprises an N-substrate, a deep P-well formed on the substrate, and an N-well formed on the deep P-well. A deep p-type region and a shallow p-type region are ion-implanted in the N-well. The deep p-type region is connected to the shallow p-type region. An n-type region is ion-implanted in the deep p-type region to be electrically shorted with the deep p-type region and be used as a drain. Another n-type region is also ion-implanted at one side of the shallow p-type region to be used as a source. The present invention can apply the same voltage to the deep P-well and the N-well on the N-substrate by adding in a triple well architecture so that the leakage current capably generated can be reduced to minimum, thereby effectively reducing end voltages when performing the operation of erasing, simplifying the design complexity of a charge pump circuit required by the whole structure, and enhancing the operating efficiency.

I claim:  
     
         1 . A fabricating method of a low-voltage channel write/erase flash memory cell, comprising mainly the steps of: 
 a. ion-implanting a deep P-well in an N-substrate;    b. ion-implanting an N-well in said deep P-well;    c. ion-implanting a shallow p-type region on the surface of said N-well;    d. growing a tunnel oxide on said shallow p-type region and depositing a poly-Si layer;    e. etching said tunnel oxide and said poly-Si layer;    f. etching out an ONO film on said etched tunnel oxide and said etched poly-Si layer;    g. depositing a poly-Si layer on said ONO film;    h. etching all grown layers and deposited layers on said tunnel oxide to form a rectangular stacked layer with exposed regions of said tunnel oxide region at two sides thereof;    i. performing oxidation to form a smiling effect oxide between said rectangular stacked layer and the surface of said N-well;    j. ion-implanting a deep p-type region at one side of said rectangular stacked layer and in said N-well; and    k. ion-implanting a plurality of n-type regions in said N-well and at two sides of said rectangular stacked layer.    
     
     
         2 . The fabricating method of a flash memory cell as claimed in  claim 1 , wherein said deep p-type region in said Step j is connected to one side of said shallow p-type region, and the implanted depth of said deep p-type region is larger than that of said shallow p-type region.  
     
     
         3 . The fabricating method of a flash memory cell as claimed in  claim 1 , wherein one of said n-type regions in said Step k is disposed in said deep p-type region.  
     
     
         4 . The fabricating method of a flash memory cell as claimed in  claim 1  further comprising the following steps: 
 l. depositing a poly-Si layer to cover said rectangular stacked layer and two sides thereof;  
 m. etching said poly-Si layer disposed at one side of said rectangular stacked layer to form a contact hole so as to expose said N-well having said deep p-type region and said n-type region thereon; and  
 n. providing a metal contact in said etched contact hole of said poly-Si layer to join said N-well having said deep p-type region and said n-type region thereon.  
 
     
     
         5 . The fabricating method of a flash memory cell as claimed in  claim 1 , wherein said p-type semiconductors and said n-type semiconductors in each step can interchange each other, e.g., an npn structure can be replaced with a pnp structure.  
     
     
         6 . A structure of a low-voltage channel write/erase flash memory cell, comprising mainly: 
 an N-substrate;    a deep P-well formed on said substrate;    an N-well formed on said deep P-well, a deep p-type region and a shallow p-type region being ion-implanted at predetermined positions in said N-well; and    a stacked gate disposed above said N-well.    
     
     
         7 . The structure of a flash memory cell as claimed in  claim 6 , wherein an oxide is further disposed between said N-well and said stacked gate.  
     
     
         8 . The structure of a flash memory cell as claimed in  claim 7 , wherein a smiling effect pattern is etched out between said stacked gate and said oxide.  
     
     
         9 . The structure of a flash memory cell as claimed in  claim 6 , wherein an n-type region is further ion-implanted in said deep p-type region in said N-well to be used as a drain.  
     
     
         10 . The structure of a flash memory cell as claimed in  claim 6 , wherein the implanted depth of said deep p-type region in said N-well is larger than that of said shallow p-type region in said N-well.  
     
     
         11 . The structure of a flash memory cell as claimed in  claim 6 , wherein said deep p-type region in said N-well is connected to one end of said shallow p-type region.  
     
     
         12 . The structure of a flash memory cell as claimed in  claim 6 , wherein an n-type region is further disposed at the other side of said shallow p-type region in said N-well to be used as a source.  
     
     
         13 . The structure of a flash memory cell as claimed in  claim 6 , wherein said n-type region implanted in said deep p-type region is connected to said deep p-type region via an electrical short circuit.  
     
     
         14 . The structure of a flash memory cell as claimed in  claim 13 , wherein said electrical short circuit is formed by using a metal contact to penetrate a junction of said n-type region in said deep p-type region and said deep p-type region.  
     
     
         15 . The structure of a flash memory cell as claimed in  claim 13 , wherein said electrical short circuit is formed by using a metal contact to connect said exposed n-type region in said deep p-type region with said deep p-type region.  
     
     
         16 . The structure of a flash memory cell as claimed in  claim 6 , wherein said n-type semiconductors and said p-type semiconductors can interchange each other, e.g., an npn structure can be replaced with a pnp structure.