Method for fabricating semiconductor memory

Abstract

In a semiconductor memory having a number of stacked capacitor memory cells each having a cylindrical lower electrode which is in the form of a cylinder having an open top and a closed bottom, an upper end of a partition, which is formed of an insulating material between adjacent cylindrical lower electrodes, has an sharpened tip end and an inclined surface descending from the sharpened tip end toward each adjacent cylindrical lower electrode. With this arrangement, it is possible to prevent silicon grains of a hemi-spherical grain silicon from nidating on the partition, thereby prevent a short-circuiting between the adjacent cylindrical lower electrodes, without reducing the capacitance of the memory cell.

1 . In a semiconductor memory having a number of stacked capacitor memory cells each having a cylindrical lower electrode which is in the form of a cylinder having an open top and a closed bottom and which is formed of a doped polysilicon having a predetermined thickness, said cylindrical lower electrode having a hemi-spherical grain silicon formed on an inner surface of said cylindrical lower electrodes, wherein an upper end of a partition, which is formed of an insulating material between adjacent cylindrical lower electrodes, has a shape preventing a nidation of a silicon grain of said hemi-spherical grain silicon.  
     
     
         2 . A semiconductor memory claimed in  claim 1  wherein said upper end of said partition has an inclined surface.  
     
     
         3 . A semiconductor memory claimed in  claim 1  wherein said upper end of said partition is convex.  
     
     
         4 . A semiconductor memory claimed in  claim 1  wherein said upper end of said partition has a projecting center portion.  
     
     
         5 . A semiconductor memory claimed in  claim 1  wherein said partition is so configured that said upper end of said partition constitutes an apex.  
     
     
         6 . A semiconductor memory claimed in  claim 1  wherein said partition is continuously formed, and the continuously formed partition has a continuously formed upper end.  
     
     
         7 . A semiconductor memory claimed in  claim 1  wherein said cylindrical lower electrode has an exposed outer wall surface.  
     
     
         8 . A semiconductor memory claimed in  claim 1  wherein a gutter is formed between said partition and said cylindrical lower electrode.  
     
     
         9 . A semiconductor memory claimed in  claim 8  wherein an outer wall surface of said cylindrical lower electrode is exposed in said gutter.  
     
     
         10 . A semiconductor memory claimed in  claim 8  wherein said gutter has a width larger than the size of one silicon grain of said hemi-spherical grain silicon formed on said inner surface of said cylindrical lower electrode.  
     
     
         11 . A semiconductor memory claimed in  claim 10  wherein said gutter has a depth not larger than a half of the depth of said partition.  
     
     
         12 . A semiconductor memory claimed in  claim 4  wherein a gutter is formed between said partition and said cylindrical lower electrode.  
     
     
         13 . A semiconductor memory claimed in  claim 12  wherein an outer wall surface of said cylindrical lower electrode is exposed in said gutter.  
     
     
         14 . A semiconductor memory claimed in  claim 12  wherein said gutter has a width larger than the size of one silicon grain of said hemi-spherical grain silicon formed on said inner surface of said cylindrical lower electrode.  
     
     
         15 . A semiconductor memory claimed in  claim 14  wherein said gutter has a depth not larger than a half of the depth of said partition.  
     
     
         16 . A semiconductor memory claimed in  claim 5  wherein a gutter is formed between said partition and said cylindrical lower electrode, and an outer wall surface of said cylindrical lower electrode is exposed in said gutter.  
     
     
         17 . A semiconductor memory claimed in  claim 16  wherein said gutter has a width larger than the size of one silicon grain of said hemi-spherical grain silicon formed on said inner surface of said cylindrical lower electrode.  
     
     
         18 . A semiconductor memory claimed in  claim 17  wherein said gutter has a depth not larger than a half of the depth of said partition.  
     
     
         19 . A method for forming a semiconductor memory having a number of stacked capacitor memory cells each having a cylindrical lower electrode in the form of a cylinder having an open top and a closed bottom, the method including the steps of depositing a stacked layer of an insulating layer and an oxide film on a semiconductor substrate, forming on said stacked layer a lower electrode in the form of a cylinder having an open top and a closed bottom and formed of a doped polysilicon, by means of a resist processing, forming a hemi-spherical grain silicon on an inner surface of said cylindrical lower electrode, forming an insulating film to form a partition filling up between adjacent cylindrical lower electrodes, and etching an oxide film in an upper end of said partition by an acid.  
     
     
         20 . A method claimed in  claim 19  wherein said etching by said acid etches the oxide film in the upper end of said partition by an excessive acid.