Metal oxide semiconductor transistor circuit and semiconductor integrated circuit using the same

Abstract

A select circuit switches a connection from a gate terminal of an NMOS transistor or a substrate voltage terminal to a semiconductor substrate or well by a Select signal. At this time, a voltage of the substrate voltage terminal is set to be lower than a gate voltage in an OFF state. Consequently, when the semiconductor substrate or well is connected to the gate terminal in an active state, the off-current can be reduced to 10 −10 A/μm. When the substrate voltage terminal is connected to the semiconductor substrate or well in a standby state, the off-current can be further reduced to 10 −12 A/μm. Thus, leakage currents in the standby state and leakage currents flowing from the power supply voltage terminal to the ground voltage terminal in an active state can be suppressed.

What is claimed is:  
     
         1 . A MOS transistor circuit comprising: 
 switching means for electrically switching a connection of a semiconductor substrate or well with which a MOS transistor is formed to either a gate terminal of the MOS transistor or a substrate voltage terminal for the semiconductor substrate or well.    
     
     
         2 . The MOS transistor circuit according to  claim 1 , wherein 
 when the MOS transistor is a first MOS transistor the switching means are constituted by: 
 a second MOS transistor whose source and drain terminals are connected to the semiconductor substrate or well and a gate terminal, and  
 a third MOS transistor whose source and drain terminals are connected to the semiconductor substrate or well and a substrate voltage terminal.  
   
     
     
         3 . The MOS transistor circuit according to  claim 2 , wherein 
 the MOS transistor connected to a terminal having a lower potential out of the gate terminal and the substrate voltage terminal out of the second MOS transistor and the third MOS transistor is an n-type MOS transistor, and    the MOS transistor connected to a terminal having a higher potential out of the gate terminal and the substrate voltage terminal out of the second MOS transistor and the third MOS transistor is a p-type MOS transistor.    
     
     
         4 . The MOS transistor circuit according to  claim 3 , wherein 
 the switching means switches a connection in response to a switching signal, and    the gate terminal of the second MOS transistor and the gate terminal of the third MOS transistor are connected to a switching signal input terminal for the switching signal.    
     
     
         5 . The MOS transistor circuit according to  claim 2 , 
 the absolute value of the threshold voltage of the second MOS transistor and that of the third MOS transistor are higher than the absolute value of the threshold voltage of the first MOS transistor.    
     
     
         6 . The MOS transistor circuit according to  claim 1 , wherein 
 the switching means switches a connection in response to switching of the MOS transistor circuit between an active state and a standby state.    
     
     
         7 . The MOS transistor circuit according to  claim 6 , wherein 
 the switching means switches a connection so that the semiconductor substrate or well is electrically connected to the gate terminal in the active state while the semiconductor substrate or well is electrically connected to the substrate voltage terminal in the standby state.    
     
     
         8 . The MOS transistor circuit according to  claim 1 , wherein 
 the switching means switches a connection in response to the change in a gate voltage of the MOS transistor.    
     
     
         9 . The MOS transistor circuit according to  claim 8 , wherein 
 the switching means switches a connection so that the semiconductor substrate or well is electrically connected to the gate terminal when the gate voltage is a voltage at which the MOS transistor conducts while the semiconductor substrate or well is electrically connected to the substrate voltage terminal when the gate voltage is a voltage at which the MOS transistor does not conduct.    
     
     
         10 . The MOS transistor circuit according to  claim 1 , wherein 
 the voltage of the substrate voltage terminal is a voltage at which the absolute value of the threshold voltage of the MOS transistor is increased when the semiconductor substrate or well is electrically connected to the substrate voltage terminal.    
     
     
         11 . A CMOS logic circuit using the MOS transistor circuit according to  claim 1  comprising: 
 a first MOS transistor circuit where the MOS transistor is a p-type MOS transistor, and  
 a second MOS transistor circuit where the MOS transistor is an n-type MOS transistor.  
 
     
     
         12 . The CMOS logic circuit according to  claim 11 , wherein 
 the semiconductor substrate or well with which the p-type MOS transistor constituting first switching means, which is means for switching the first MOS transistor circuit, is formed is connected to a first substrate voltage terminal, which is a substrate voltage terminal of the first MOS transistor circuit, while the semiconductor substrate or well with which the n-type MOS transistor constituting the first switching means is formed is connected to a ground voltage terminal, and    the semiconductor substrate or well with which the p-type MOS transistor constituting second switching means, which is means for switching the second MOS transistor circuit, is formed is connected to a power supply voltage terminal while the semiconductor substrate or well with which the n-type MOS transistor constituting the second switching means is formed is connected to a second substrate voltage terminal, which is a substrate voltage terminal of the second MOS transistor circuit.    
     
     
         13 . The CMOS logic circuit according to  claim 11 , wherein 
 the semiconductor substrate or well with which the p-type MOS transistor constituting the first switching means, which is means for switching the first MOS transistor circuit is formed is connected to the first substrate voltage terminal, which is a substrate voltage terminal of the first MOS transistor circuit, while the semiconductor substrate or well with which the n-type MOS transistor constituting the first switching means is formed is connected to the second substrate voltage terminal, which is a substrate voltage terminal of the second MOS transistor circuit, and    the semiconductor substrate or well with which the p-type MOS transistor constituting the second switching means, which is means for switching the second MOS transistor circuit, is formed is connected to the first substrate voltage terminal while the semiconductor substrate or well with which the n-type MOS transistor constituting the second switching means is formed is connected to the second substrate voltage terminal.    
     
     
         14 . The CMOS logic circuit according to  claim 11 , wherein 
 a first switching signal input terminal, which is a switching signal input terminal for the first MOS transistor circuit, and a second switching signal input terminal, which is a switching signal input terminal for the second MOS transistor circuit, are connected.    
     
     
         15 . The CMOS logic circuit according to  claim 14 , wherein 
 the switching signal is generated by 
 a p-type MOS transistor where source and drain terminals thereof are connected to the first switching signal input terminal and the second switching signal input terminal and the first substrate voltage terminal, which is a substrate voltage terminal of the first MOS transistor circuit, while a gate terminals is connected to an input terminal of the CMOS logic circuit and  
 an n-type MOS transistor where source and drain terminals are connected to the first switching signal input terminal and the second switching signal input terminal and the second substrate voltage terminal, which is a substrate voltage terminal of the second MOS transistor circuit, while a gate terminal is connected to the input terminal of the CMOS logic circuit.  
   
     
     
         16 . The CMOS logic circuit according to  claim 15 , wherein 
 the absolute value of the threshold voltage of the p-type MOS transistors generating the switching signal is set to be higher than the difference between a voltage of the first substrate voltage terminal and a voltage of the power supply voltage terminal and lower than the difference between a voltage of the first substrate voltage terminal and a voltage of the ground voltage terminal, and    the absolute value of the threshold voltage of the n-type MOS transistor generating the switching signal is set to be higher than the difference between a voltage of the second substrate voltage terminal and a voltage of the ground voltage terminal and lower than the difference between a voltage of the second substrate voltage terminal and a voltage of the power supply voltage terminal.    
     
     
         17 . The CMOS logic circuit according to  claim 15 , wherein 
 the semiconductor substrate or well with which the p-type MOS transistor generating the switching signal is formed is connected to the first substrate voltage terminal, and    the semiconductor substrate or well with which the n-type MOS transistor generating the switching signal is formed is connected to the second substrate voltage terminal.    
     
     
         18 . A latching circuit comprising the CMOS logic circuit according to  claim 11 .  
     
     
         19 . A flip-flop comprising the CMOS logic circuit according to  claim 11 .  
     
     
         20 . The flip-flop according to  claim 19  comprising a master-stage latching circuit and a slave-stage latching circuit, wherein 
 the CMOS logic circuit is used in the configuration of either the master-stage latching circuit or slave-stage latching circuit.  
 
     
     
         21 . A data storage circuit for once storing data of an operation stopping circuit when power supply is stopped to the operation stopping circuit, wherein 
 the latching circuit according to  claim 18  is included in the configuration.    
     
     
         22 . A data storage circuit for once storing data of an operation stopping circuit when power supply is stopped to the operation stopping circuit, wherein 
 the flip-flop according to  claim 19  is included in the configuration.    
     
     
         23 . A data storage circuit for once storing data of an operation stopping circuit when power supply is stopped to the operation stopping circuit, wherein 
 the flip-flop according to  claim 20  is included in the configuration.    
     
     
         24 . The data storage circuit according to  claim 23 , wherein 
 there is provided power supply stopping means for stopping power supply to a latching circuit not using the CMOS logic circuit out of a master-stage latching circuit and a slave-stage latching circuit constituting the flip-flop when power supply is stopped to the operation stopping circuit.