US2002179952A1PendingUtilityA1

MIM capacitor and manufacturing method therefor

Assignee: MURATA MANUFACTURING COPriority: Dec 11, 2000Filed: Nov 21, 2001Published: Dec 5, 2002
Est. expiryDec 11, 2020(expired)· nominal 20-yr term from priority
Inventors:Hidefumi Nakata
H10P 14/6314H10P 14/662H10W 20/496H10D 1/684H10D 1/692H10D 1/696H01G 4/33
32
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A downsized, high-capacity MIM capacitor provided on a compound semiconductor includes a lower electrode comprising a plurality of metal layers including a top metal layer, an upper electrode, and a dielectric layer positioned between the lower electrode and the upper electrode. The entire surface of the top metal layer is oxidized to form an insulating metal oxide layer.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . An MIM capacitor comprising: 
 a lower electrode comprising a plurality of metal layers including a top metal layer;    an upper electrode; and    a dielectric layer positioned between said lower electrode and said upper electrode,    wherein the entire surface of the top metal layer is oxidized to form an insulating metal oxide layer.    
     
     
         2 . An MIM capacitor according to  claim 1 , wherein the top metal layer comprises a material selected from transition metals and alloys thereof which are capable of forming insulating layers by oxidation.  
     
     
         3 . An MIM capacitor according to  claim 1 , wherein the top metal layer comprises titanium.  
     
     
         4 . An MIM capacitor according to  claim 1 , wherein said dielectric layer comprises silicon nitride.  
     
     
         5 . An MIM capacitor according to  claim 4 , wherein the surface of said dielectric layer is oxidized to form an oxidized silicon nitride layer.  
     
     
         6 . A method of manufacturing an MIM capacitor, comprising: 
 providing a lower electrode comprising a plurality of metal layers including a top metal layer;    oxidizing the top metal layer of the lower electrode by heating at a temperature between 200 and 400° C.;    providing a dielectric layer on the oxidized top metal layer; and    providing an upper layer on the dielectric layer.    
     
     
         7 . A method of manufacturing an MIM capacitor according to  claim 6 , wherein the dielectric layer is formed of silicon nitride.  
     
     
         8 . A method of manufacturing an MIM capacitor according to  claim 7 , further comprising oxidizing the dielectric layer by heating at between 200 and 400° C.  
     
     
         9 . A method of manufacturing an MIM capacitor according to  claim 6 , wherein the oxidizing of the top metal layer and the oxidizing of the dielectric layer are performed in an atmosphere containing oxygen.  
     
     
         10 . A method of manufacturing an MIM capacitor according to  claim 6 , wherein the oxidizing of the top metal layer and the oxidizing of the dielectric layer are performed in an atmosphere containing an oxygen plasma or ozone.  
     
     
         11 . A microwave monolithic integrated circuit comprising an MIM capacitor as set forth in  claim 1 .  
     
     
         12 . A microwave monolithic integrated circuit comprising an MIM capacitor prepared by a manufacturing method as set forth in claim  6 .

Join the waitlist — get patent alerts

Track US2002179952A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.