Vertical heterojunction bipolar transistor

Abstract

A heterojunction bipolar transistor ( 20, 60 ) is provided with a silicon (Si) base region ( 34, 74 ) that forms a semiconductor junction with a multilayer emitter ( 38 ) having a thin gallium arsenide (GaAs) emitter layer ( 36, 72 ) proximate the base region ( 34, 74 ) and a distal gallium phosphide (GaP) emitter layer ( 40, 66 ). The GaAs emitter layer ( 36, 72 ) is sufficiently thin, preferably less than 200 Å, so as to be coherently strained. In one embodiment, the GaP emitter layer includes a doped region ( 70 ) that serves as the emitter and an undoped region ( 68 ) on which the intrinsic portion of the transistor ( 60 ) is formed.

What is claimed is:  
     
         1 . A vertical heterojunction bipolar transistor comprising: 
 a gallium phosphide layer (GaP) configured to exhibit a first conductivity type, said GaP layer forming a first portion of a multilayer emitter;    a gallium arsenide (GaAs) layer formed in contact with said GaP layer, said GaAs layer forming a second portion of said multilayer emitter;    a silicon (Si) base region of a second conductivity type formed in contact with said GaAs layer; and    a Si collector region of said first conductivity type formed adjacent to said Si base region.    
     
     
         2 . A vertical heterojunction bipolar transistor as claimed in  claim 1  wherein said GaAs layer is less than 200 Å thick.  
     
     
         3 . A vertical heterojunction bipolar transistor as claimed in  claim 1  wherein said GaAs layer is sufficiently thin so as to be coherently strained.  
     
     
         4 . A vertical heterojunction bipolar transistor as claimed in  claim 1  wherein said GaAs layer is configured so as not to exhibit said second conductivity type.  
     
     
         5 . A vertical heterojunction bipolar transistor as claimed in  claim 1  wherein a base-emitter transistor junction located at an interface between said Si base region and said GaAs layer is substantially free of interdiffusion.  
     
     
         6 . A vertical heterojunction bipolar transistor as claimed in  claim 1  wherein said GaAs layer and said GaP layer are epitaxially grown.  
     
     
         7 . A vertical heterojunction bipolar transistor as claimed in  claim 1  wherein said transistor additionally comprises a Si substrate positioned underneath said GaP layer.  
     
     
         8 . A vertical heterojunction bipolar transistor as claimed in  claim 7  wherein said GaAs layer is a first GaAs layer and said transistor additionally comprises a second GaAs layer between said Si substrate and said GaP layer.  
     
     
         9 . A vertical heterojunction bipolar transistor as claimed in  claim 1  wherein: 
 said GaP layer is configured to have a first region doped to exhibit said first conductivity type, said first region of said GaP layer being in contact with said GaAs layer and forming said first portion of said multilayer emitter; and  
 said GaP layer is configured to have a second region in contact with said second GaAs layer, said second region being substantially undoped.  
 
     
     
         10 . A vertical heterojunction bipolar transistor as claimed in  claim 9  wherein said first GaP region is intrinsic to said heterojunction bipolar transistor and said second GaP layer is extrinsic to said heterojunction bipolar transistor.  
     
     
         11 . A vertical heterojunction bipolar transistor as claimed in  claim 1  wherein: 
 said GaP layer is configured to have a first region doped to exhibit said first conductivity type, said first region of said GaP layer being in contact with said GaAs layer and forming said first portion of said multilayer emitter; and  
 said GaP layer is configured to have a second region in contact with said second GaAs layer, said second region being substantially insulative.  
 
     
     
         12 . A vertical heterojunction bipolar transistor as claimed in  claim 1  wherein: 
 said GaAs layer is formed over said GaP layer;  
 said Si base region is formed over said GaAs layer; and  
 said Si collector region is formed over said Si base region.  
 
     
     
         13 . A vertical heterojunction bipolar transistor as claimed in  claim 1  additionally comprising an emitter contact coupled to one of said GaAs layer and said GaP layer, a base contact coupled to said Si base region, and a collector contact coupled to said Si collector region, wherein said emitter contact is an outermost one of said emitter, base, and collector contacts, and said collector contact in an innermost one of said emitter, base, and collector contacts.  
     
     
         14 . A vertical heterojunction bipolar transistor comprising: 
 a first non-silicon layer exhibiting a first conductivity type and a bandgap wider than silicon, said first non-silicon layer forming a first layer of a multilayer emitter;    a second non-silicon layer in contact with said first non-silicon layer, said second non-silicon layer forming a second layer of said multilayer emitter;    a silicon (Si) base layer of a second conductivity type formed in contact with said second non-silicon layer, wherein an base-emitter transistor junction is formed at a boundary between said second non-silicon layer and said base layer and wherein said base-emitter transistor junction is substantially free of interdiffusion; and    a Si collector of said first conductivity type formed adjacent to said base layer.    
     
     
         15 . A vertical heterojunction bipolar transistor as claimed in  claim 14  wherein: 
 said first non-silicon layer is configured to have a first region doped to exhibit said first conductivity type, said first region being intrinsic to said heterojunction bipolar transistor; and  
 said first non-silicon layer is configured to have a second region which is substantially insulative, said second region being extrinsic to said heterojunction bipolar transistor.  
 
     
     
         16 . A vertical heterojunction bipolar transistor as claimed in  claim 14  wherein said second non-silicon layer is gallium arsenide (GaAs).  
     
     
         17 . A vertical heterojunction bipolar transistor as claimed in  claim 14  wherein said second non-silicon layer is coherently strained between said silicon base layer and said first non-silicon layer.  
     
     
         18 . A vertical heterojunction bipolar transistor as claimed in  claim 17  wherein said second non-silicon layer is gallium arsenide (GaAs) and has a thickness of less than 200 Å.  
     
     
         19 . A vertical heterojunction bipolar transistor as claimed in  claim 14  wherein said first non-silicon layer is gallium phosphide (GaP).  
     
     
         20 . A vertical heterojunction bipolar transistor as claimed in  claim 14  wherein said transistor additionally comprises a Si substrate, wherein said first non-silicon layer is formed over said Si substrate.  
     
     
         21 . A vertical heterojunction bipolar transistor as claimed in claim  20  wherein: 
 said first non-silicon layer is formed substantially of gallium phosphide (GaP);  
 said first non-silicon layer is configured to have a first region doped to exhibit said first conductivity type, said first region being in contact with said second non-silicon layer; and  
 said first non-silicon layer is configured to have a second region proximate said Si substrate, said second region not being doped to exhibit said first conductivity type.