Adjustable I/O timing from externally applied voltage

Abstract

An integrated circuit, including but not limited to a memory device, receives an externally provided voltage signal and selectively adjusts the timing of internal control signals. An external signal selects between two possible pre-determined delay paths. The delay paths are adjusted using fuse circuitry which can be programmed by the manufacturer prior to implementation by a user. The delay path adjustment feature is particularly applicable to adjusting output signal timing to allow the integrated circuit to be operated in an environment which requires slower communications speeds. The same integrated circuit, therefore, can also be implemented in an environment which allows for faster communications speeds.

What is claimed is:  
     
         1 . An integrated circuit memory device comprising: 
 data output circuitry for providing data read from the memory device to an external connection;    an adjustable delay circuit, comprising: 
 a first input node to receive an input signal;  
 a second input node to receive an encoded control signal;  
 an output node to provide an output signal; and  
 a plurality of possible delay paths for communicating the input signal to the output node, the plurality of possible delay paths including a plurality of delay circuits, each delay circuit including at least two output connections and a select circuit, at least one of the at least two output connections being electrically common with the output node, wherein the encoded control signal is decoded by each of the select circuits to determine which of the at least two output connections the input signal will be communicated along en route to the output node, wherein an operating speed of the data output circuitry is adjusted by the particular delay path along which the input signal is communicated to the output node.  
   
     
     
         2 . The integrated circuit of  claim 1  wherein lengths of the plurality of possible delay paths are predetermined and adjusted using fuse circuitry.  
     
     
         3 . The integrated circuit of  claim 1  wherein the plurality of delay circuits are serially connected.  
     
     
         4 . An integrated circuit memory device comprising: 
 data output circuitry for providing data read from the memory device to an external connection;    an adjustable delay circuit, comprising: 
 a first input node to receive an input signal;  
 a second input node to receive an encoded control signal;  
 an output node to provide an output signal; and  
 a plurality of possible delay paths for communicating the input signal to the output node, the plurality of possible delay paths including a plurality of delay circuits, each delay circuit including at least two output connections and a select circuit, at least one of the at least two output connections being electrically common with the output node, wherein the encoded control signal is decoded by each of the select circuits to determine, by selecting one of the at least two output connections, how many serially-connected delay circuits the input signal will be communicated through en route to the output node, wherein an operating speed of the data output circuitry is adjusted by the particular delay path along which the input signal is communicated to the output node.  
   
     
     
         5 . The integrated circuit memory device of  claim 4 , further comprising a fuse circuit for selecting between first and second possible delay paths.  
     
     
         6 . The integrated circuit memory device of  claim 5 , wherein the first delay path operates the integrated circuit memory device at a first communication speed, and the second delay path operates the integrated circuit memory device at a second communication speed.  
     
     
         7 . The integrated circuit memory device of  claim 4 , further comprising an enable circuit to couple an externally provided voltage signal to the adjustable delay circuit.  
     
     
         8 . The integrated circuit memory device of  claim 4  wherein the memory device is a synchronous random access memory (SRAM).  
     
     
         9 . A data processing system comprising: 
 a processor; and    a memory device coupled to the processor, the memory device comprising: 
 an adjustable delay circuit, comprising: 
 a first input node to receive an input signal;  
 a second input node to receive an encoded control signal;  
 an output node to provide an output signal; and  
 a plurality of possible delay paths for communicating the input signal to the output node, the plurality of possible delay paths including a plurality of delay circuits, each delay circuit including at least two output connections and a select circuit, at least one of the at least two output connections being electrically common with the output node, wherein the encoded control signal is decoded by each of the select circuits to determine which of the at least two output connections the input signal will be communicated along en route to the output node, wherein an operating speed of the data output circuitry is adjusted by the particular delay path along which the input signal is communicated to the output node.  
 
   
     
     
         10 . The data processing system of  claim 9  wherein the plurality of delay circuits are serially connected and wherein the adjustable delay circuit selects between a first delay path that operates the integrated circuit memory device at a first communication speed, and a second delay path that operates the integrated circuit memory device at a second communication speed.  
     
     
         11 . The data processing system of  claim 9  wherein the memory device is a synchronous random access memory (SRAM).  
     
     
         12 . The data processing system of  claim 1   1  wherein the SRAM operates as a cache memory for the processor.  
     
     
         13 . A method of operating a memory integrated circuit device, comprising: 
 providing data read from the memory device to an external connection;    providing a plurality of delay circuits within an adjustable delay circuit of the memory device, each delay circuit including a select circuit and at least two output connections;    selecting, in each delay circuit, between a first internal communication delay path along one of the at least two output connections and a second internal communication delay path along another of the at least two output connections; and    controlling the speed at which the data is provided to the external connection based on the particular selection between the first internal communication delay path and the second internal communication delay path.    
     
     
         14 . The method of  claim 13 , comprising using series-coupled delay paths defining the first and second internal communication paths.  
     
     
         15 . A method of selecting a data output speed of a memory device, comprising: 
 reading data from the memory device to an external connection;    providing a plurality of delay circuits within an adjustable delay circuit of the memory device each having a select circuit and at least two output connections;    adjusting the adjustable delay circuit, such that the adjustable delay circuit couples an input signal by decoding an encoded control signal in one of the select circuits to a delay output via a first delay path along one of the at least two output connections, and the delay circuit couples the input signal by decoding the control signal in another of the select circuits to the delay output via a second delay path along another of the at least two output connections; and    controlling a speed of a data output circuit in response to a signal provided at the delay output to control the rate of data provided to the external connection.    
     
     
         16 . The method of  claim 15  further comprising encoding a control signal using a fuse circuit.  
     
     
         17 . The method of  claim 16  wherein the encoded control signal is a multiple bit signal for selecting between the first and second delay paths.  
     
     
         18 . A method of operating a data processing system, the system including a processor, a memory device coupled to the processor and having an input, and data output circuitry for reading data from the memory device to the processor, the method comprising: 
 encoding a control signal;    receiving an input signal at the memory device;    providing a plurality of delay circuits, each delay circuit including a select circuit and at least two output connections;    decoding the encoded control signal at each of the select circuits;    delaying communication of the input signal to an output node by an amount related to the encoded control signal to adjust the operating speed of the data output circuitry.    
     
     
         19 . The method of  claim 18 , wherein the delaying is effected by communicating the input signal to an output node on a selected one of a plurality of paths.  
     
     
         20 . The method of  claim 19 , wherein the paths are defined at least in part by a state of at least one fuse element.  
     
     
         21 . An integrated circuit for inclusion in a memory device of a data processing system, the data processing system also including a processor and data output circuitry for reading data from the memory device to a point accessible by the processor, the integrated circuit comprising: 
 means for providing an input signal by which the data output circuitry is controllable;    an adjustable delay circuit for receiving the input signal and providing a responsive output signal at an output node, the adjustable delay circuit including a plurality of possible delay paths for communicating the input signal to the output node, the plurality of possible delay paths including a plurality of delay circuits, each delay circuit including at least two output connections and a select circuit, at least one of the at least two output connections being electrically common with the output node; and    means for providing an encoded control signal; and    wherein the encoded control signal is decoded by each of the select circuits to determine which of the at least two output connections the input signal will be communicated along en route to the output node.    
     
     
         22 . The integrated circuit of  claim 21  wherein lengths of the plurality of possible delay paths are predetermined and adjustable using fuse circuitry.  
     
     
         23 . The integrated circuit of  claim 22  wherein the plurality of delay circuits are serially connected.  
     
     
         24 . The data processing system of  claim 21  wherein the memory device is a synchronous random access memory (SRAM).