Differential current mode gain stage and methods of using the same

Abstract

A differential current mode gain stage and methods of using the same are provided. The gain stage may comprise a plurality of transistors. The gain stage is configured to keep at least one transistor of the plurality of transistors out of saturation mode while operating with a supply voltage of less than two base-emitter voltages, receiving an input signal, generating a first output signal if the input signal comprises a common mode signal, and generating a second output signal if the input signal comprises a differential signal, the second output signal having a larger amplitude than the first output signal.

What is claimed is:  
     
         1 . A gain stage in an amplifier, the gain stage comprising a plurality of transistors, the gain stage configured to keep at least one transistor of the plurality of transistors out of saturation mode while operating with a supply voltage of less than two base-emitter voltages, receiving an input signal, generating a first output signal if the input signal comprises a common mode signal, and generating a second output signal if the input signal comprises a differential signal, the second output signal having a larger amplitude than the first output signal.  
     
     
         2 . The gain stage of  claim 1 , configured to operate with a supply voltage of about 1.2 volts.  
     
     
         3 . The gain stage of  claim 1 , configured to operate with a supply voltage of about 1.0 volt.  
     
     
         4 . The gain stage of  claim 1 , wherein the input signal comprises a first input current and a second input current, the first input current having a larger amplitude than the second input current.  
     
     
         5 . The gain stage of  claim 1 , wherein the input signal comprises a first input current and a second input current, the first input current having a different phase than the second input current.  
     
     
         6 . The gain stage of  claim 1 , wherein at least a portion of the plurality of transistors implement a common mode feedback loop, the common mode feedback loop configured to limit an amplitude of an amplified output signal if the input signal comprises a common mode signal.  
     
     
         7 . The gain stage of  claim 1 , configured to output a small gain signal if the input signal comprises a small differential signal.  
     
     
         8 . The gain stage of  claim 7 , wherein the small gain signal associated with the small differential input signal is substantially equal to a beta parameter of at least one transistor of the plurality of transistors in the gain stage.  
     
     
         9 . The gain stage of  claim 1 , wherein the gain stage enters a merged common mode and differential mode operation if the input signal comprises a large differential input signal.  
     
     
         10 . The gain stage of  claim 1 , wherein a large differential input signal causes a shift in a common mode level.  
     
     
         11 . The gain stage of  claim 1 , configured to output at least one output current that is not limited by a fixed bias input current.  
     
     
         12 . The gain stage of  claim 1 , wherein a signal output by the gain stage is limited only by the supply voltage and at least one beta value of the transistors.  
     
     
         13 . The gain stage of  claim 1 , comprising: 
 a first transistor comprising a first collector terminal, a first base terminal and a first emitter terminal, the first collector terminal coupled to a first output terminal, the first base terminal coupled to a first power source, and the first emitter terminal coupled to a first resistor;    a second transistor comprising a second collector terminal, a second base terminal and a second emitter terminal, the second collector terminal coupled to a second output terminal, the base terminal coupled to a second power source, and the second emitter terminal coupled to a second resistor;    a third transistor comprising a third collector terminal, a third base terminal and a third emitter terminal, the third collector terminal coupled to the first power source, the third base terminal coupled to a third power source, and the third emitter terminal coupled to a third resistor;    a fourth transistor comprising a fourth collector terminal, a fourth base terminal and a fourth emitter terminal, the fourth collector terminal coupled to the second power source, the fourth base terminal coupled to the third power source, and the fourth emitter terminal coupled to a fourth resistor;    a fifth transistor comprising a fifth collector terminal, a fifth base terminal and a fifth emitter terminal, the fifth collector terminal coupled to the third power source, the fifth base terminal coupled to the third power source, and the fifth emitter terminal coupled to the first resistor; and    a sixth transistor comprising a sixth collector terminal, a sixth base terminal and a sixth emitter terminal, the sixth collector terminal coupled to the third power source, the sixth base terminal coupled to the third power source, and the sixth emitter terminal coupled to a second resistor.    
     
     
         14 . An operational amplifier comprising: 
 an input stage configured to receive at least one input signal and operate with a supply voltage of less than two base-emitter voltages;    an intermediate stage coupled to the input stage, the intermediate stage comprising a plurality of transistors, the intermediate stage configured to keep at least one transistor of the plurality of transistors out of saturation mode while operating with a supply voltage of less than two base-emitter voltages, receiving a signal from the input stage, generating a first output signal if the signal from the input stage comprises a common mode signal, and generating a second output signal if the signal from the input stage comprises a differential signal, the second output signal having a larger amplitude than the first output signal; and    an output stage coupled to the intermediate stage, the output stage configured to receive the first or the second output signal from the intermediate stage.    
     
     
         15 . The operational amplifier of  claim 14 , wherein the operational amplifier is configured to operate with a supply voltage of about 1.2 volts.  
     
     
         16 . The operational amplifier of  claim 14 , wherein the operational amplifier is configured to operate with a supply voltage of about 1.0 volts.  
     
     
         17 . A method of providing a signal gain, the method comprising: 
 operating with a supply voltage of less than two base-emitter voltages volts;    generating a first output signal if an input signal comprises a common mode signal;    generating a second output signal if the input signal comprises a differential signal, wherein the second output signal has a larger amplitude than the first output signal; and    keeping the at least one transistor in a circuit out of saturation mode while generating the first and second output signals.