Vertical field effect transistor and manufacturing method thereof

Abstract

A vertical field effect transistor ( 1 ) and a method of manufacturing thereof are disclosed, in which a buried layer ( 3 ) of a conduction type opposite to that of a substrate ( 2 ) are formed to a predetermined depth in the substrate ( 2 ) by ion implantation. The bottom of a of recesses ( 2 a ) for forming a protrusion ( 2 b ) on the substrate ( 2 ) is located within the corresponding one of the buried layer ( 3 ). The width of the recess ( 2 a ) is set smaller than the width of the buried layer ( 3 ). The surface of the protrusion ( 2 b ) and the bottom of the recess ( 2 a ) are formed with impurities regions ( 4 a, 4 b ; 5 a , 5 b ) constituting a source and a drain, respectively. A channel length (L) of the channel region formed on the side wall of the protrusion ( 2 b ) is defined by the distance between the buried layer ( 3 ) and the impurities regions ( 5 a , 5 b ) on the surface of the protrusion ( 2 b ).

What is claimed is:  
     
         1 . A vertical field effect transistor, comprising: 
 a substrate;    a protrusion which is formed on the substrate and whose side wall of said protrusion serves as a channel region: 
 a buried layer of a conduction type opposite to that of said substrate formed to a predetermined depth of said substrate by ion implantation;  
 a recess for forming said protrusion,its bottom being located within said buried layer and a width of said recess smaller being selected to be than the width of said buried layer; and  
 an impurity region making up each of a source and a drain formed on the surface of said protrusion and on the bottom surface of said recesses, wherein a channel length is set by the distance between said buried layer and said impurity region on the surface of said protrusion.  
   
     
     
         2 . A vertical field effect transistor according to  claim 1 , further comprising on a channel region of its side wall: 
 a first gate insulating film;    a floating gate electrode;    a second gate insulating film; and    a control gate electrode.    
     
     
         3 . A method of manufacturing a vertical field effect transistor, comprising the steps of: 
 forming a buried layer of a second conduction type by ion implantation to a predetermined depth in a semiconductor substrate of a first conduction type;    forming a recess having a width smaller than the width of said buried layer and having the bottom thereof located within said buried layer of said semiconductor substrate;    forming a gate electrode through a gate insulating film on the side wall of a protrusion formed by said recess; and    forming an impurity region making up a source and a drain on the surface of said protrusion and on the bottom surface of said recess.    
     
     
         4 . A method of manufacturing a vertical field effect transistor according to  claim 2 , wherein said buried layer is thermally diffused after ion implantation.  
     
     
         5 . A method of manufacturing a vertical field effect transistor according to  claim 2 , 
 wherein said buried layer is formed by ion implantation using a mask formed on an insulating film, and    wherein a said wall insulating film is formed on said insulating film patterned by said mask, and thereafter said recess is formed with said insulating layer and said side wall insulating film as a mask.