Semiconductor memory device with memory cells having same characteristics and manufacturing method for the same

Abstract

In a method of manufacturing a semiconductor memory device, a lower electrode film is formed on a semiconductor substrate via an interlayer insulating film. A ferroelectric film is formed on the lower electrode layer while heating the lower electrode layer uniformly in the cell array region. An upper electrode film is formed on the ferroelectric film. Ferroelectric capacitors are formed in a memory cell array region. Each of the ferroelectric capacitors includes the lower electrode film, the ferroelectric film and the upper electrode film.

What is claimed is:  
     
         1 . A method of manufacturing a semiconductor memory device, comprising the steps of: 
 (a) forming a lower electrode film on a semiconductor substrate via an interlayer insulating film;    (b) forming a ferroelectric film on said lower electrode layer while heating said lower electrode layer;    (c) forming an upper electrode film on said ferroelectric film; and    (d) forming ferroelectric capacitors in a memory cell array region, each of said ferroelectric capacitors comprising said lower electrode film, said ferroelectric film and said upper electrode film.    
     
     
         2 . The method according to  claim 1 , wherein said lower electrode film is formed of material containing at least one of platinum, iridium, iridium oxide, ruthenium and ruthenium oxide.  
     
     
         3 . The method according to  claim 1 , further comprising the step of: 
 (e) forming thermally conductive routes in said memory cell array region and a connection region outside said memory cell array region to pass through said interlayer insulating film to said semiconductor substrate, and to be connected with said lower electrode film, and    wherein said (b) forming step comprises the step of: 
 heating said lower electrode film via said thermally conductive routes.  
   
     
     
         4 . The method according to  claim 3 , wherein said (e) forming step of: 
 forming contact plugs for said routes passing through a portion of said interlayer insulating film each time said interlayer insulating film portion is formed.    
     
     
         5 . The method according to  claim 3 , wherein said heating comprises the step of: 
 heating said semiconductor substrate.    
     
     
         6 . The method according to  claim 3 , wherein a density of said thermally conductive routes in said memory cell array region is substantially the same as that of said thermally conductive routes in said connection region  
     
     
         7 . The method according to  claim 3 , wherein said (e) forming step further comprises the step of: 
 forming additional thermally conductive routes in said interlayer insulating film in a peripheral circuit region outside said connection region to be connected with said thermally conductive routes in said connection region.    
     
     
         8 . The method according to  claim 1 , wherein said (b) forming step comprises the step of: 
 heating said semiconductor substrate to about 450° C.    
     
     
         9 . The method according to  claim 1 , wherein said (a) forming step comprises the step of: 
 forming said lower electrode film to extend outside said memory cell array region.    
     
     
         10 . A semiconductor memory device having a memory cell array region, a peripheral circuit region and a connection region between said memory cell array region and said peripheral circuit region, comprising: 
 ferroelectric capacitors formed on a semiconductor substrate via an interlayer insulating film in said memory cell array region; and    conductive films formed on said interlayer insulating film in said connection region, and    wherein said conductive films are connected with said semiconductor substrate via conductive routes passing through said interlayer insulating film, respectively.    
     
     
         11 . The semiconductor memory device according to  claim 10 , wherein a layer for said conductive films is formed when a lower electrode layer for said ferroelectric capacitors is formed.  
     
     
         12 . The semiconductor memory device according to  claim 11 , wherein said lower electrode layer is formed of material containing at least one of platinum, iridium, iridium oxide, ruthenium and ruthenium oxide.  
     
     
         13 . The semiconductor memory device according to  claim 10 , further comprising MOS transistors formed on said semiconductor substrate in said memory cell array region and said connection region, and 
 wherein each of said ferroelectric capacitors is connected with one of said MOS transistors formed in said memory cell array region and each of said conductive films is connected with one of said MOS transistors formed in said connection region.    
     
     
         14 . The semiconductor memory device according to  claim 10 , wherein a density of said ferroelectric capacitors is substantially the same as that of said conductive films.  
     
     
         15 . The semiconductor memory device according to  claim 10 , further comprising additional conductive films formed in said peripheral circuit region, and 
 wherein said additional conductive films are connected with any of said conductive routes in said connection region.    
     
     
         16 . The semiconductor memory device according to  claim 10 , wherein said semiconductor memory device is a logic circuit embedded FeRAM.  
     
     
         17 . The semiconductor memory device according to  claim 10 , wherein said semiconductor memory device is a logic circuit embedded non-volatile SRAM.  
     
     
         18 . A method of manufacturing a semiconductor memory device, comprising the steps of: 
 (a) forming MOS transistors in a memory cell array region and a connection region outside said memory cell array region, wherein a density of said MOS transistors in said memory cell array region is substantially the same as that of said MOS transistors in said connection region;    (b) forming an interlayer insulating film to cover said MOS transistors while forming thermally conductive routes, each of which extends from one of said MOS transistors to pass through said interlayer insulating film;    (c) forming a lower electrode film on a semiconductor substrate via said interlayer insulating film to be connected with said thermally conductive routes;    (d) forming a ferroelectric film on said lower electrode layer while heating said lower electrode layer;    (e) forming an upper electrode film on said ferroelectric film; and    (f) forming ferroelectric capacitors in said memory cell array region, each of said ferroelectric capacitors comprising said lower electrode film, said ferroelectric film and said upper electrode film.    
     
     
         19 . A method of manufacturing a semiconductor memory device, comprising the steps of: 
 (a) forming MOS transistors in a memory cell array region and a connection region outside said memory cell array region, wherein a density of said MOS transistors in said memory cell array region is substantially the same as that of said MOS transistors in said connection region;    (b) forming an interlayer insulating film to cover said MOS transistors while forming thermally conductive routes, each of which extends from one of said MOS transistors to pass through said interlayer insulating film;    (c) forming a lower electrode film on a semiconductor substrate via said interlayer insulating film to be connected with said thermally conductive routes;    (d) forming a ferroelectric film on said lower electrode layer while heating said lower electrode layer via said thermally conductive routes on a side of said semiconductor substrate;    (e) forming an upper electrode film on said ferroelectric film; and    (f) forming ferroelectric capacitors in said memory cell array region, each of said ferroelectric capacitors comprising said lower electrode film, said ferroelectric film and said upper electrode film.    
     
     
         20 . The method according to  claim 19 , wherein said (b) forming step further comprises the step of: 
 forming additional thermally conductive routes in said interlayer insulating film in a peripheral circuit region outside said connection region to be connected with said thermally conductive routes in said connection region.