Field-effect transistor and manufacture thereof

Abstract

A source and a drain of a field-effect transistor are formed so as to fulfill a specified physical relationship to upper and lower gates thereof and thereby parasitic capacitance that hampers its high-speed operation is minimized. The filed-effect transistor includes a second support substrate, a lower gate that is embedded in an insulator formed on the second support substrate, an insulating layer formed on the lower gate, a semiconductor layer formed on the insulating layer, an insulating layer formed on the semiconductor layer, an upper gate formed on the insulating layer, as well as a source electrode, a drain electrode, an upper gate electrode, and a lower gate electrode all of which are isolated from one another by the insulating layer.

What is claimed is:  
     
         1 . A double-gate field-effect transistor having a structure that comprises: 
 a first gate that is embedded in an insulator on a support substrate and contacts with an insulating layer on said insulator;    a source and a drain formed on a semiconductor layer on said insulating layer; and    a second gate that is formed on an embedded insulating layer formed on said semiconductor layer,    wherein said first gate and said second gate are opposite to each other through the intermediaries of said insulating layer, said semiconductor layer, and said embedded insulating layer.    
     
     
         2 . A double-gate field-effect transistor according to  claim 1 , wherein wiring of four electrodes that are each connected to said source, said drain, said first gate, and said second gate is formed.  
     
     
         3 . A double-gate field-effect transistor according to  claim 1 , wherein an adjustment hole that reaches as deep as said support substrate is provided in a depressed manner in order to position said first gate and said second gate to each other.