Method and system for providing security to processors

Abstract

There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are thereafter ignored. In addition, if it is determined that an internal memory access is occurring, the contents of such an access can be masked to prevent unauthorized viewing of the memory contents via an external memory bus. In addition, a programmable security bit may be set to disable the dumping of flash memory contents, allowing only the erasing of the flash memory.

We claim:  
     
         1 . A method of securing the contents of the memory in a microprocessor system comprising: 
 determining, after a power-on/reset of the microprocessor, the status of an external addressing status pin; and    preventing accesses to external addresses if said external addressing pin is set.    
     
     
         2 . The method of  claim 1  further comprising: 
 ignoring subsequent changes to the status of the external addressing status pin.  
 
     
     
         3 . The method of  claim 1  further comprising: 
 masking the memory output ports such that the results of a memory access is not accessible through monitoring of the memory output ports.  
 
     
     
         4 . The method of  claim 1  wherein said microprocessor system comprises a microcontroller.  
     
     
         5 . A method of securing the contents of the memory in a microprocessor system comprising: 
 determining, upon a power-on/reset of the microprocessor, the status of a programmable security bit; and    disabling flash memory commands in the event that the programmable security bit is set, such that a disabled flash memory command has no effect on the microprocessor system.    
     
     
         6 . The method of  claim 5  wherein said disabling step allows for mass erasure of the contents of the flash memory.  
     
     
         7 . The method of  claim 6  wherein said disabling step disables all flash memory commands except mass erasure.  
     
     
         8 . The method of  claim 5  wherein said microprocessor system comprises a microcontroller.  
     
     
         9 . A method of securing the contents of the memory in a processor system comprising: 
 determining whether a particular memory access requests access to external memory; and    in the event that the memory access does not request access to external memory, masking the memory output ports such that the result of the memory access is not accessible through monitoring of the processor.    
     
     
         10 . The method of  claim 9  wherein said determining and masking steps occur with each processor access to memory.  
     
     
         11 . The method of  claim 9  further comprising: 
 performing a power-on/reset of the processor; and  
 ascertaining the status of an external addressing status pin;  
 wherein said determining step follows said ascertaining step; and  
 said masking step masks the memory output ports until the processor experiences a power-on/reset.  
 
     
     
         12 . The method of  claim 11  further comprising: 
 preventing memory accesses to external addresses.  
 
     
     
         13 . The method of  claim 11  wherein said masking step comprises: 
 outputting a predetermined value to the memory output port.  
 
     
     
         14 . The method of  claim 13  wherein said predetermined value is a logical low level.  
     
     
         15 . The method of  claim 13  wherein said predetermined value is a logical high level.  
     
     
         16 . A processor with security features comprising: 
 means for determining the status of a pin indicating the status of external memory accesses; and    means for preventing accesses to external memory.    
     
     
         17 . The processor of  claim 16  wherein 
 said means for determining comprises a software program configured to monitor the status of said pin indicating the status of external memory accesses.  
 
     
     
         18 . The processor of  claim 16  wherein said means for preventing comprises a software program configured to prevent access to external memory.