Device with epitaxial base

Abstract

A high voltage electrical device ( 20 ), having a substrate layer ( 22 ), base layer ( 24 ) and top layer ( 26 ), provides high voltage properties in excess of 1000V. Slicing a wafer ( 28 ) from an ingot ( 30 ) created in by monocrystalline growth forms the substrate layer ( 22 ), and this high quality crystal is used as the high resistivity layer in the device ( 20 ). The base layer ( 24 ) is a highly doped, low resistivity, epitaxial layer deposited on the lower surface ( 32 ) of the substrate layer ( 22 ) at a fast rate greater than approximately 2 microns/minute. The top layer ( 26 ) is a diffusion layer diffused into an upper surface ( 34 ) of the substrate layer ( 22 ). To control stress in the wafer ( 28 ), the epitaxial base is doped with germanium.

What is claimed is:  
     
         1 . An electrical device for use in high voltage applications, the device comprising: 
 a high resistivity substrate layer having a substrate conductive type, the substrate layer being formed of a high purity monocrystalline semiconductor material by crystalline growth method into an ingot which is sliced to at least a desired thickness of the substrate layer, and the substrate layer having first and second spaced and generally parallel surfaces;    a low resistivity base epitaxial layer of semiconductor material including a base dopant and having an epitaxial conductive type, the base epitaxial layer being formed contiguous with the substrate layer first surface; and    a low resistivity top layer having a top layer conductive type and being formed contiguous with the substrate layer second surface.    
     
     
         2 . The electrical device according to  claim 1  wherein the first surface has a first surface area, and the second surface has a second surface area smaller than the first service area to form a positive bevel angle at an edge of the device.  
     
     
         3 . The electrical device according to  claim 1  wherein the top layer comprises a top diffusion layer of semiconductor material and another dopant diffused into a top surface of the device.  
     
     
         4 . The electrical device according to  claim 1  wherein the top layer comprises a top epitaxial layer deposited on the second surface.  
     
     
         5 . The electrical device according to  claim 1  wherein the substrate conductive type comprises an N −  conductive type, the epitaxial conductive type comprises a P +  conductive type, and the top layer conductive type comprises an N +  conductive type.  
     
     
         6 . The electrical device according to  claim 1  wherein the substrate conductive type comprises an P −  conductive type, the epitaxial conductive type comprises a N +  conductive type, and the top layer conductive type comprises an P +  conductive type.  
     
     
         7 . The electrical device according to  claim 1  wherein the substrate layer comprises a thickness in the range of approximately 50 microns to approximately 130 microns.  
     
     
         8 . The electrical device according to  claim 1  wherein the electrical device is rated at approximately 1700V at approximately 7 amps.  
     
     
         9 . The electrical device according to  claim 1  wherein the base epitaxial layer comprises a thickness in the range of approximately 250 microns to approximately 400 microns and the top layer comprises a generally centrally located recess minimizing, in a central portion of the electrical device, the distance between the top layer and the base epitaxial layer.  
     
     
         10 . The electrical device according to  claim 1  wherein the base dopant comprises boron, and the base epitaxial layer further includes a stress relief dopant.  
     
     
         11 . The electrical device according to  claim 10  wherein the stress relief dopant comprises germanium.  
     
     
         12 . A semiconductor wafer having a plurality of electrical devices formed thereon, the wafer comprising: 
 a top side; a bottom side;    a high resistivity substrate layer having a substrate conductive type, the substrate layer being formed of a high purity monocrystalline semiconductor material and the substrate layer having first and second spaced and generally parallel surfaces;    a low resistivity base layer of semiconductor material including a dopant and having a base conductive type, the base layer being formed contiguous with the substrate layer first surface and the bottom side;    a low resistivity top layer having a top layer conductive type and being formed contiguous with the substrate layer second surface and the top side;    a grid of intersecting channels formed in a selected one of the top side and the bottom side, the channels separating the electrical devices from each other.    
     
     
         13 . The wafer according to  claim 12  wherein the base layer comprises an epitaxial base layer, and the base conductive type comprises P type.  
     
     
         14 . The wafer according to  claim 12  wherein the base layer comprises an epitaxial base layer, and the base conductive type comprises N type.  
     
     
         15 . The wafer according to  claim 12  wherein the selected side comprises the top side.  
     
     
         16 . The wafer according to  claim 12  wherein the wafer is generally circular and comprises approximately 1000 electrical devices.  
     
     
         17 . The wafer according to  claim 12  wherein the channels comprise etched moats, and the semiconductor material comprises silicon.  
     
     
         18 . A method for fabricating a plurality of high voltage electrical devices, the method comprising: 
 growing a high resistivity monocrystalline ingot from a semiconductor material having a substrate conductive type;    slicing at least one wafer having a desired thickness from the ingot, the wafer providing a substrate including first and second spaced and generally parallel surfaces;    forming a highly doped, low resistivity, base layer contiguous with the first surface of the substrate, and the base layer having a base layer conductive type;    forming a low resistivity top layer contiguous with the second surface of the substrate, and the top layer having a top layer conductive type; and    dividing the wafer to form separate electrical devices.    
     
     
         19 . The method according to  claim 18  wherein forming the base layer comprises depositing the base layer on the first surface.  
     
     
         20 . The method according to  claim 19  wherein depositing the base layer comprises depositing the base layer at a rate of greater than approximately 2 microns per minute.  
     
     
         21 . The method according to  claim 18  wherein dividing the wafer comprises etching the wafer to form a grid of moats and separating the diodes along the moats, and forming the top layer comprises diffusing a dopant into the second surface.  
     
     
         22 . The method according to  claim 18  further comprising grinding the substrate to a desired substrate thickness after the base layer is formed, thereby forming a high resistivity substrate layer.  
     
     
         23 . The method according to  claim 18  further comprising doping the base layer with a stress control dopant, and adjusting the concentration of the stress control dopant so that the wafer is substantially flat.  
     
     
         24 . An electrical device rated at, at least approximately 1000V, the diode comprising: 
 a high resistivity substrate layer having a substrate conductive type, the substrate layer being formed of a high purity monocrystalline semiconductor material and the substrate layer having first and second spaced and generally parallel surfaces;    a low resistivity base epitaxial layer including a dopant and having an epitaxial conductive type, the base epitaxial layer being formed contiguous with the substrate layer first surface; and    a low resistivity top layer having a top layer conductive type and being formed contiguous with the substrate layer second surface.    
     
     
         25 . The electrical device according to  claim 24  further comprising an edge termination including a bevel angle greater than approximately 15°.  
     
     
         26 . The electrical device according to  claim 24  wherein the top layer comprises a generally centrally located recess minimizing, in a central portion of the electrical device, the distance between the top layer and the epitaxial layer.