Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits

Abstract

An interconnect substrate has formed thereon a first plurality of conductive leads and a second plurality of conductive leads. A plurality of cells are formed in the substrate, each cell having a number of bonding pads formed on the surface of the substrate above the region of the substrate in which the cell is formed, thereby to allow a plurality of integrated circuit chips and electrical components to be attached to the substrate and electrically connected to the cells. Devices and programming elements in the substrate or in integrated circuits mounted on the substrate allow selected connections to be formed between selected ones of the conductive leads to be connected electrically thereby to allow selected components mounted on the substrate to be electrically interconnected. Other devices in the substrate or in integrated circuits mounted on the substrate allow testing of the components mounted on the substrate to determine their performance and the checking of the integrity of the connections formed between conductive leads.

What is claimed is:  
     
         1 . Structure comprising: 
 a substrate;    a first plurality of conductive leads formed on said substrate in a first direction;    a second plurality of conductive leads formed on said substrate in a second direction substantially different from said first direction;    a number of programming elements/for allowing selected conductive leads to be connected to other conductive leads or for allowing non-selected conductive leads to be disconnected from other conductive leads; and    a plurality of cells formed in said substrate, each cell having a number of bonding pads formed on the surface of said substrate above the region of said substrate in which said cell is formed thereby to allow a plurality of integrated circuit chips and/or electronic components to be attached to and electrically connected to said plurality of cells.    
     
     
         2 . Structure comprising: 
 a substrate;    a first plurality of conductive leads formed on said substrate in a first direction;    a second plurality of conductive leads formed on said substrate in a second direction substantially different from said first direction;    a number of programming elements for allowing selected conductive leads to be connected to other conductive leads or for allowing non-selected conductive leads to be disconnected from other conductive leads;    a plurality of cells formed in said substrate, each cell having a number of bonding pads formed on the surface of said substrate above the region of said substrate in which said cell is formed thereby to allow a plurality of integrated circuit chips or electronic components to be attached to and electrically connected to said plurality of cells; and    a plurality of devices formed in said substrate for programming all or a portion of said programming elements.    
     
     
         3 . Structure as in  claim 2  wherein said substrate comprises-a semiconductor substrate.  
     
     
         4 . Structure as in  claim 2  wherein said number of programming elements for allowing selected conductive leads to be connected to other conductive leads allows selected conductive leads in one direction to be connected to conductive leads formed in the other direction.  
     
     
         5 . Structure as  claim 2  wherein said structure includes 
 a first dielectric layer formed on said substrate beneath said first plurality of conductive leads; and  
 a second dielectric layer formed between said first plurality of conductive leads and said second plurality of conductive leads;  
 wherein said programming elements comprise regions of said second dielectric layer containing a number of regions of an antifuse dielectric material particularly amenable to being formed into a conductive path by the application to said antifuse dielectric material of a voltage having a value equal to or greater than a selected value.  
 
     
     
         6 . Structure as in  claim 2  wherein said plurality of cells are arranged in rows and columns.  
     
     
         7 . Structure as in  claim 6   wherein said first direction is parallel to said rows of cells and said second direction is parallel to said columns of cells; and    wherein at least one of said first plurality of conductive leads has a length so as to extend across at least two of the cells in a selected row and at least one of said second plurality of conductive leads has a length so as to extend across at least two of the cells in a given column.    
     
     
         8 . Structure as in  claim 7  wherein said first plurality of conductive leads comprises leads with differing lengths such that for each row of cells at least one lead extends across at least two cells in a row.  
     
     
         9 . Structure as in  claim 8  wherein said second plurality of conductive leads comprise leads with differing lengths such that for each column of cells at least one lead extends over at least two cells in a column.  
     
     
         10 . Structure as in  claim 6   wherein said first plurality of conductive leads contains leads such that at least one lead extends over two adjacent cells in each row and another lead extends over all the cells in each row; and    wherein said second plurality of conductive leads contains leads such that at least one lead extends over two adjacent cells in each column and another lead extends over all cells in each column.    
     
     
         11 . Structure as in  claim 6   wherein said first plurality of conductive leads contains a first multiplicity of conductive leads of different lengths which extend over different numbers of cells in each row; and    wherein said second plurality of conductive leads contains a second multiplicity of conductive leads of different lengths which extend over different numbers of cells in each column.    
     
     
         12 . Structure as in  claim 2   wherein said first plurality of conductive leads and said second plurality of conductive leads are formed on different levels and are separated by dielectric.    
     
     
         13 . Structure as in  claim 12  including 
 a plurality of devices formed in said semiconductor material, each of said plurality of devices being connected on a one-to-one basis between means for supplying power and selected ones of the conductive leads in said first plurality of conductive leads and said second plurality of conductive leads so that a selected voltage can be applied to a first selected conductive lead and another voltage can be applied to a second selected conductive lead such that a voltage difference is created to program the programming element connecting said first selected conductive lead and said second selected conductive lead thereby to form at said interconnection a conductive path between said first selected conductive lead and said second selected conductive lead.  
 
     
     
         14 . Structure as in  claim 12  including 
 a first plurality of IO leads connected to said substrate for the transmission to and from said substrate of selected signals for use in determining which selected conductive leads are to be connected by programming a selected set of said programming elements.  
 
     
     
         15 . Structure comprising: 
 a substrate;    a first plurality of conductive leads formed on said substrate in a first direction;    a second plurality of conductive leads formed on said substrate in a second direction substantially different from said first direction;    a plurality of cells formed in said substrate, each cell having a number of bonding pads formed on the surface of said substrate above the region of said substrate in which said cell is formed thereby to allow a plurality of integrated circuit chips or electronic components to be attached to and electrically connected to said plurality of cells; and    a plurality of devices formed in said substrate for testing said conductive leads or said plurality of integrated circuit chips or electronic components to be attached to and electrically connected to said plurality of cells.    
     
     
         16 . Structure as in  claim 5  including 
 a selected plurality of IO leads for use in transmitting selected signals;  
 a number of semiconductor circuit chips or electronic components connected on the bonding pads formed on the surface of said substrate above the region of said substrate in which a selected number of said plurality of cells are formed;  
 a multiplicity of devices formed in said substrate, said devices being connected to a selected number of said pads thereby to allow signals applied at said plurality of IO input leads to test the electrical circuits contained in said semiconductor chips attached to bonding pads on said substrate or to test the integrity of conductive leads on said substrate.  
 
     
     
         17 . Structure as in  claim 15  including 
 means for providing access by a user to a first plurality of IO leads on said structure and to a second plurality of IO leads on said structure;  
 first means for storing data input into said structure by a user;  
 means for sampling selected pads formed on said cells in said structure to determine the state of the electrical components attached to said selected pads;  
 means for comparing the data sampled from said pads to the data stored in said first means for storing to determine whether or not a match between said sampled and stored data has occurred;  
 second means for storing the data available on said pads in response to a match being detected between the data stored in said first means for storing and the sampled data; and  
 means for outputting the data stored in said second means for storing.  
 
     
     
         18 . Structure as in  claim 15  including: 
 a selected plurality of IO leads for use in transmitting selected signals; a  
 a multiplicity of devices formed in said substrate, said devices being connected to a selected number of said pads thereby to allow signals applied at said plurality of IO input leads to test the integrity of conductive leads on said substrate.  
 
     
     
         19 . Structure comprising: 
 an interconnect substrate;    a plurality of component contacts formed on said interconnect substrate for receipt of electronic components;    a plurality of electrically conductive traces formed on said interconnect substrate, each trace being electrically connected to a corresponding one of said component contacts; and    at least one integrated circuit mounted on a selected portion of said interconnect substrate, said at least one integrated circuit containing a plurality of conductive leads, at least one of said conductive leads being electrically connected to a corresponding one of said electrically conductive traces formed on said interconnect substrate, said at least one integrated circuit also containing a plurality of programming elements programmable to form electrically conductive paths between selected ones of said corresponding conductive leads on said at least one integrated circuit, said at least one integrated circuit thereby being configurable by a user to interconnect selected electrically conductive traces on said interconnect substrate to achieve a desired electrical function from the electronic components to be connected to said interconnect substrate.    
     
     
         20 . Structure as in  claim 19   wherein said interconnect substrate contains more than one layer of conductive traces.    
     
     
         21 . Structure as in  claim 19   wherein at least some of said plurality of component contacts comprise a plurality of pads on said interconnect substrate, each pad being appropriate for receipt of a conductive lead of an electronic component.    
     
     
         22 . Structure as in  claim 21   wherein each pad comprises conductive material and is electrically connected to a corresponding one of said electrically conductive traces.    
     
     
         23 . Structure as in  claim 21   including a multiplicity of electronic components mounted on said interconnect substrate, each electronic component possessing at least two electrical leads, each electrical lead contacting a corresponding pad selected from said plurality of pads.    
     
     
         24 . Structure as in  claim 23   wherein said multiplicity of electronic components comprises at least one integrated circuit.    
     
     
         25 . Structure as in  claim 21   wherein at least some of said pads on said interconnect substrate comprise trace pads, each trace pad being connected to a corresponding one of said plurality of electrically conductive traces formed on said interconnect substrate.    
     
     
         26 . Structure as in  claim 2   wherein each trace pad is connected by a conductive lead to a conductive via formed through said interconnect substrate, said conductive via containing conductive material therein so as to form an electrical contact with a corresponding one of said electrically conductive traces formed on said interconnect substrate.    
     
     
         27 . Structure as in  claim 19   wherein said interconnect substrate comprises: 
 a first portion thereof containing conductive traces for interconnecting electronic components formed thereon without the use of a programmable integrated circuit; and  
 a second portion thereof containing at least one programmable interconnect circuit for interconnecting electronic components formed on at least said second portion of said interconnect substrate.  
   
     
     
         28 . Structure as in  claim 27   including means for transmitting control signals to said at least one programmable interconnect circuit to control the configuration of said at least one programmable interconnect circuit so as to control the interconnection of the conductive traces formed on said interconnect substrate.    
     
     
         29 . Structure comprising: 
 an interconnect substrate;    a plurality of component contacts formed on said interconnect substrate for receipt of electronic components;    a plurality of electrically conductive traces formed on said interconnect substrate, each trace being electrically connected to a corresponding one of said component contacts; and    at least one integrated circuit mounted on a selected portion of said interconnect substrate, said at least one integrated circuit containing a plurality of conductive leads, at least one of said conductive leads being electrically connected to a corresponding one of said electrically conductive traces on said interconnect substrate, said at least one integrated circuit containing active devices for testing said conductive leads and said conductive traces or said electronic components to be mounted on corresponding one of said plurality of component contacts.    
     
     
         30 . Structure as in  claim 29   including at least one programmable integrated circuit mounted on said interconnect substrate to interconnect selected traces formed on said interconnect substrate.    
     
     
         31 . A programmable interconnect chip for use in interconnecting electronic components formed on an interconnect substrate, said chip comprising: 
 a first set of conductive leads formed in a first direction across the surface of said chip, each of said conductive leads comprising one or more conductive segments, portions of selected ones of said segments being connected to pads on the surface of said programmable interconnect chip, each of said pads being adapted for contact to corresponding contact on the interconnect substrate;    a second set of conductive leads formed on said programmable interconnect chip in a second direction not parallel to said first direction, each conductive lead in said second set of conductive leads comprising one or more segments; and    means for electrically interconnecting selected ones of said conductive leads.    
     
     
         32 . Structure as in  claim 31   wherein said programmable interconnect chip includes: 
 programmable elements;  
 means for electrically connecting selected ones of the segments of conductive leads by means of said programmable elements; and  
 means for programming said programmable elements in said interconnect chip so as to form desired interconnections between selected contacts on said interconnect substrate.  
   
     
     
         33 . A diagnostic and test chip for use in testing electronic components and conductive traces formed on an interconnect substrate, said diagnostic and test chip comprising: 
 a selected plurality of IO leads for use in transmitting selected signals;    a multiplicity of devices formed in said diagnostic and test chip, said devices being connected to a selected number of said electronic components and said conductive traces thereby to allow signals to be applied to said plurality of IO input leads to test the electronic components and the conductive traces contained on said interconnect substrate.    
     
     
         34 . Structure as in  claim 33  including a number of semiconductor circuit chips or electronic components connected on bonding pads formed on the surface of said substrate.  
     
     
         35 . A diagnostic and test chip for use in testing electronic components and/or conductive traces formed on an interconnect substrate, said diagnostic and test chip comprising: 
 means for providing access by a user to a first plurality of IO leads to said diagnostic and test chip and to a second plurality of IO leads to said diagnostic and test chip;    first means for storing data input into said test chip by a user;    means for sampling selected electronic components formed on said interconnect substrate to determine the state of these electronic components;    means for comparing the data sampled from the said electronic components to the data stored in said first means for storing data to determine whether or not a match between said sampled and stored data has occurred;    second means for storing the data available from said electronic components in response to a match being detected between the data stored in said first means for storing and the sampled data; and    means for outputting the data stored in said second means for storing.    
     
     
         36 . Structure comprising: 
 a substrate;    a first plurality of conductive leads formed on said substrate in a first direction;    a second plurality of conductive leads formed on said substrate in a second direction substantially different from said first direction; and    a plurality of cells formed in said substrate, each cell having a number of bonding pads formed on the surface of said substrate above the region of said substrate in which said cell is formed thereby to allow a plurality of integrated circuit chips or electronic components to be attached to and electrically connected to said plurality of cells.