Method for forming a silicide gate stack for use in a self-aligned contact etch

Abstract

A method for forming a gate stack having a silicide layer that can subsequently undergo a SAC etch is disclosed. The present method provides a layer of insulating material on top of the silicide layer. The insulating material is sufficient to protect the gate stack, including the silicide layer when the low-resistance gate stack is used in subsequent self-aligned contact etch processes.

What is claimed as new and desired to be protected by Letters Patent of the United States is:  
     
         1 . A gate structure for a semiconductor device, comprising: 
 a gate oxide formed on a semiconductor substrate;    a conductive gate formed on said gate oxide;    a silicide layer formed on said conductive gate; and    an etch protecting cap formed over a top surface of said silicide gate, said cap being sufficient to protect said conductive gate and silicide layer from being etched during a self-aligned contact etching process, employing said gate structure.    
     
     
         2 . The gate structure of  claim 1 , wherein said silicide layer is formed by a salicide process.  
     
     
         3 . The gate structure of  claim 2 , wherein said cap is formed of silicon-based insulator.  
     
     
         4 . The gate structure of  claim 3 , wherein said insulator is selected from the group consisting of silicon nitride and silicon oxide.  
     
     
         5 . The gate structure of  claim 3 , wherein said cap has a thickness within the range of approximately 1000 to 2000 Angstroms.  
     
     
         6 . The gate structure of  claim 2 , wherein said conductive gate is formed of polysilicon.  
     
     
         7 . The gate structure of  claim 6 , wherein said polysilicon gate has a thickness within the range of approximately 500 to 1500 Angstroms.  
     
     
         8 . The gate structure of  claim 2 , wherein said silicide layer is formed from a metal selected from the group consisting of cobalt, titanium, tungsten, tantalum, molybdenum, and platinum.  
     
     
         9 . The gate structure of  claim 2 , wherein said silicide layer has a thickness within the range of approximately 200 to 500 Angstroms.  
     
     
         10 . The gate structure of  claim 2  further comprising an insulating spacer on side walls of said gate structure.  
     
     
         11 . The gate structure of  claim 10 , wherein said insulating spacer is formed of silicon nitride.  
     
     
         12 . A method for forming a gate structure for a semiconductor device, comprising: 
 forming a gate oxide on a semiconductor substrate;    forming a conductive gate on said gate oxide;    forming a silicide layer on said conductive gate by a salicide method; and    forming an etch protective cap over a top surface of said silicide gate, said cap being sufficient to protect said conductive gate and silicide layer from being etched during a self-aligned contact etching process, employing said gate structure.    
     
     
         13 . The method of  claim 12 , wherein said cap is formed of silicon-based insulator.  
     
     
         14 . The method of  claim 13 , wherein said insulator is selected from the group consisting of silicon nitride and silicon oxide.  
     
     
         15 . The method of  claim 13 , wherein said cap has a thickness within the range of approximately 1000 to 2000 Angstroms.  
     
     
         16 . The method of  claim 12 , wherein said conductive gate is formed of polysilicon.  
     
     
         17 . The method of  claim 16 , wherein said polysilicon gate has a thickness within the range of approximately 500 to 1500 Angstroms.  
     
     
         18 . The method of  claim 12 , wherein said silicide layer is formed from a metal selected from the group consisting of cobalt, titanium, tungsten, tantalum, molybdenum, and platinum.  
     
     
         19 . The method of  claim 12 , wherein said silicide layer has a thickness within the range of approximately 200 to 500 Angstroms.  
     
     
         20 . The method of  claim 12  further comprising an insulating spacer on side walls of said gate structure.  
     
     
         21 . The method of  claim 20 , wherein said insulating spacer is formed of silicon nitride.  
     
     
         22 . The method of  claim 12 , wherein said self-aligned contact etching process comprises etching an insulating layer in said semiconductor substrate with an etchant selected from the group consisting of C 2 F 6 , CH 4 , C 3 F 8 , C 4 H 10 , C 2 F 8 , CH 2 F 2 , CHF 3 , C 2 HF 5 , and CH 3 F.  
     
     
         23 . The method of  claim 22 , wherein said etching of said insulating layer is a reactive ion etch (RIE) employing a composition comprising a CF 4 /CHF 3 /CH 2 F 2 /Ar gas mixture at volume ratio 1:1:1:8.  
     
     
         24 . A method for forming features of a semiconductor device, comprising: 
 forming a gate stack on a semiconductor substrate, said gate stack including an oxide layer provided on said substrate, a conductive layer over said oxide layer, a silicide layer over said conductive layer formed by a salicide process and a cap layer over said silicide layer; and    providing an insulating layer over said substrate and said gate stack; and    performing a self-aligned contact etch of said insulating layer using said gate stack to align said etch.    
     
     
         25 . The method of  claim 24 , wherein said step of performing a self-aligned contact etch comprises etching said insulating layer with an etchant selected from the group consisting of C 2 F 6 , CH 4 , C 3 F 8 , C 4 H 10 , C 2 F 8 , CH 2 F 2 , CHF 3 , C 2 HF 5 , and CH 3 F.  
     
     
         26 . The method of  claim 25 , wherein said etching of said insulating layer is a reactive ion etch (RIE) employing a composition comprising a CF 4 /CHF 3 /CH 2 F 2 /Ar gas mixture at volume ratio 1:1:1:8.  
     
     
         27 . The method of  claim 24 , wherein said cap layer of said gate stack is formed of silicon-based insulator.  
     
     
         28 . The method of  claim 27 , wherein said insulator is selected from the group consisting of silicon nitride and silicon oxide.  
     
     
         29 . The method of  claim 24 , wherein said cap layer of said gate stack has a thickness within the range of approximately 1000 to 2000 Angstroms.  
     
     
         30 . The method of  claim 24 , wherein said conductive layer of said gate stack is formed of polysilicon.  
     
     
         31 . The method of  claim 30 , wherein said polysilicon layer has a thickness within the range of approximately 500 to 1500 Angstroms.  
     
     
         32 . The method of  claim 24 , wherein said silicide layer is formed from a metal selected from the group consisting of cobalt, titanium, tungsten, tantalum, molybdenum, and platinum.  
     
     
         33 . The method of  claim 24 , wherein said silicide layer has a thickness within the range of approximately 200 to 500 Angstroms.  
     
     
         34 . A method for forming a gate structure for a semiconductor device, comprising: 
 forming an insulating layer over a substrate;    masking said insulating layer to define an etching area on top of said insulating layer;    etching said insulating layer at said etching area down to a top surface of said substrate to form an opening into said insulating layer;    forming a gate oxide layer on said substrate at the bottom of said opening;    depositing a polysilicon layer over said gate oxide layer;    etching said polysilicon layer to form a polysilicon gate over said gate oxide layer;    depositing a refractory metal over said polysilicon gate;    converting said refractory metal to a silicide layer over said polysilicon gate;    forming an etch protective cap over a top surface of said silicide layer; and    etching away said insulating layer to leave a gate stack comprising said oxide layer, said polysilicon gate, said silicide layer, and said protective cap.    
     
     
         35 . The method of  claim 34 , wherein said cap is sufficient to protect said conductive gate and silicide layer from being etched during a self-aligned contact etching process, employing said gate structure.  
     
     
         36 . The method of  claim 34  further comprising forming a barrier layer over said substrate prior to the formation of said insulating layer over said substrate.  
     
     
         37 . The method of  claim 36  further comprising etching away of said barrier layer.  
     
     
         38 . The method of  claim 34 , wherein said insulating layer is selected from the group consisting of BPSG, BSG, and PSG.  
     
     
         39 . The method of  claim 34 , wherein said barrier layer is TEOS.  
     
     
         40 . The method of  claim 34 , wherein etching of said insulating layer to form said opening employs a reactive ion etch (RIE).  
     
     
         41 . The method of  claim 34 , wherein etching of said insulating layer to form said opening employs a wet etch.  
     
     
         42 . The method of  claim 34 , wherein forming of said gate oxide layer further comprises growing of an oxide layer onto said opening and over said top surface of said substrate.  
     
     
         43 . The method of  claim 34 , wherein said gate oxide layer has a thickness within the range of approximately 30 to 150 Angstroms.  
     
     
         44 . The method of  claim 34 , wherein said polysilicon gate has a thickness within the range of approximately 500 to 1500 Angstroms.  
     
     
         45 . The method of  claim 34 , wherein said refractory metal is selected from the group consisting of cobalt, titanium, tungsten, tantalum, molybdenum, and platinum.  
     
     
         46 . The method of  claim 34 , wherein said silicide layer has a thickness within the range of approximately 200 to 500 Angstroms.  
     
     
         47 . The method of  claim 34 , wherein said cap is formed of silicon-based insulator.  
     
     
         48 . The method of  claim 47 , wherein said insulator is selected from the group consisting of silicon nitride and silicon oxide.  
     
     
         49 . The method of  claim 34 , wherein said cap has a thickness within the range of approximately 1000 to 2000 Angstroms.  
     
     
         50 . The method of  claim 37 , wherein said steps of etching away of said insulating layer and said barrier layer employ an etchant selected from the group consisting of C 2 F 6 , CH 4 , C 3 F 8 , C 4 H 10 , C 2 F 8 , CH 2 F 2 , CHF 3 , C 2 HF 5 , and CH 3 F.  
     
     
         51 . The method of  claim 37 , wherein said steps of etching away of said insulating layer and said barrier layer is a reactive ion etch (RIE) employing a composition comprising a CF 4 /CHF 3 /CH 2 F 2 /Ar gas mixture at volume ratio 1:1:1:8.  
     
     
         52 . The method of  claim 34  further comprising forming an insulating spacer on side walls of said gate structure.  
     
     
         53 . The method of claim  52 , wherein said insulating spacer is formed of silicon nitride.